74HCT193DB-T datasheet, PDF - EEWORLD Datasheet

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74HCT193DB-T: DescriptionBinary Counter; Categorylogic logic; File Size379KB，29 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74HCT193DB-T Overview

Binary Counter

74HCT193DB-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	,
Reach Compliance Code	compliant
Logic integrated circuit type	BINARY COUNTER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename

Nexperia.

Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use

http://www.nexperia.com

Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use

salesaddresses@nexperia.com

(email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via

salesaddresses@nexperia.com).

Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Rev. 5 — 29 January 2016

Product data sheet

1. General description

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate

up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state

synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is

pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while

CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at

any time to guarantee predictable behavior. The device can be cleared at any time by the

asynchronous master reset input (MR); it may also be loaded in parallel by activating the

asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count

down (TCD) outputs are normally HIGH. When the circuit has reached the maximum

count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.

TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,

the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.

The terminal count outputs can be used as the clock input signals to the next higher order

circuit in a multistage counter, since they duplicate the clock waveforms. Multistage

counters will not be fully synchronous, since there is a slight delay time difference added

for each stage that is added. The counter may be preset by the asynchronous parallel

load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is

loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the

conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on

the master reset (MR) input will disable the parallel load gates, override both clock inputs

and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a

reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted

as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the

use of current limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits



Input levels:



For 74HC193: CMOS level



For 74HCT193: TTL level



Synchronous reversible 4-bit binary counting



Asynchronous parallel load



Asynchronous reset



Expandable without external logic



Complies with JEDEC standard no. 7A



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V.

74HCT193DB-T Related Products

	74HCT193DB-T	74HC193D-T	74HC193DB-T	74HC193PW-T	74HC193DB	74HCT193DB	74HCT193D-T	74HC193D	74HCT193PW	74HCT193PW-T
Description	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter	Binary Counter
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Base Number Matches	1	1	1	1	1	1	1	1	1	1
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	260	260	260	260	260	NOT SPECIFIED
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	30	30	30	30	30	NOT SPECIFIED

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