74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 1 — 4 April 2013
Product data sheet
1. General description
The 74LVC138A-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary
weighted address inputs (A0, A1 and A2). When the inputs are enabled, it provides eight
mutually exclusive outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LVC138A-Q100 devices and one inverter.
The 74LVC138A-Q100 can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW
state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Mutually exclusive outputs
Output drive capability 50
transmission lines at 125
C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC138AD-Q100
74LVC138APW-Q100
74LVC138ABQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
DX
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
0
1
15
14
13
12
11
10
9
7
4
5
6
&
1
2
3
1
2
4
X/Y
0
1
2
3
4
5
6
15
14
13
12
11
10
9
7
0
G
2
0
7
15
14
13
12
11
10
9
7
2
3
2
3
4
4
5
6
&
5
6
7
EN
7
mna371
(a)
(b)
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Y0
1
2
3
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
mna372
15
14
13
12
11
10
9
7
Fig 3.
Functional diagram
74LVC138A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
2 of 15
NXP Semiconductors
74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
/9&$4
$
$
$
(
(
(
<
*1'
DDD
/9&$4
WHUPLQDO
LQGH[ DUHD
$
$
(
(
(
<
*1'
<
*1'
9
&&
<
<
<
<
<
<
$
9
&&
<
<
<
<
<
<
<
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO16 and TSSOP16
Fig 5.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y[0:7]
V
CC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
74LVC138A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
3 of 15
NXP Semiconductors
74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
Table 3.
Input
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
Function table
[1]
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
V
O
= 0 V to V
CC
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO16 packages: above 70
C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP16 packages: above 60
C
the value of P
D
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
D
derates linearly with 4.5 mW/K.
74LVC138A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
4 of 15
NXP Semiconductors
74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall
rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
output HIGH or LOW state
Conditions
Min
1.65
1.2
0
0
40
0
0
Typ
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output
voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
1.7
2.0
-
-
-
-
40 C
to +85
C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
40 C
to +125
C
Min
1.08
1.7
2.0
-
-
-
-
-
-
0.12
0.7
0.8
0.65
V
CC
-
Max
V
V
V
V
V
V
V
Unit
0.65
V
CC
-
0.35
V
CC
-
0.35
V
CC
V
input leakage V
CC
= 3.6 V; V
I
= 5.5 V or GND -
current
74LVC138A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 April 2013
5 of 15
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