M59DR032A
M59DR032B
32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory
PRELIMINARY DATA
s
SUPPLY VOLTAGE
– V
DD
= V
DDQ
= 1.65V to 2.2V: for Program,
Erase and Read
– V
PP
= 12V: optional Supply Voltage for fast
Program and Erase
s
ASYNCHRONOUS PAGE MODE READ
BGA
– Page Width: 4 words
– Page Access: 35ns
– Random Access: 100ns
s
PROGRAMMING TIME
– 10µs by Word typical
– Double Word Programming Option
TSOP48 (N)
12 x 20mm
FBGA48 (ZB)
8 x 6 solder balls
s
MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit - 28 Mbit
– Parameter Blocks (Top or Bottom location)
– Main Blocks
Figure 1. Logic Diagram
s
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
VDD VDDQ VPP
21
A0-A20
W
E
G
RP
WP
M59DR032A
M59DR032B
16
DQ0-DQ15
s
BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up
– Any combination of Blocks can be protected
– WP for Block Locking
s
s
s
s
COMMON FLASH INTERFACE (CFI)
64 bit SECURITY CODE
ERASE SUSPEND and RESUME MODES
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s
VSS
AI02544B
s
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M59DR032A: A0h
– Device Code, M59DR032B: A1h
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M59DR032A, M59DR032B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (3)
V
DD
, V
DDQ
V
PP
Parameter
Ambient Operating Temperature
(2)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Program Voltage
Value
–40 to 85
–40 to 125
–55 to 155
–0.5 to V
DDQ
+0.5
–0.5 to 2.7
–0.5 to 13
Unit
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Depends on range.
3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
DESCRIPTION
The M59DR032 is a 32 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.65V to 2.2V V
DD
supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports asynchronous page
mode from all the blocks of the memory array.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power Up. Blocks can be
unprotected to make changes in the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Re-
sume, Block Protect, Block Unprotect, Block Lock-
ing, CFI Query, are written to the memory through
a Command Interface using standard micropro-
cessor write timings.
The device is offered in TSOP48 (12 x 20 mm)
and in FBGA48 0.75 mm ball pitch packages.
When shipped all bits of the M59DR032 device are
at the logical level ‘1’.
Organization
The M59DR032 is organized as 2Mb x16 bits. A0-
A20 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs.
Reset RP is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.
Memory Blocks
The device features asymmetrically blocked archi-
tecture. M59DR032 has an array of 71 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sector-
ization are summarized in Table 7. Parameter
Blocks are located at the top of the memory ad-
dress space for the M59DR032A, and at the bot-
tom for the M59DR032B. The memory maps are
shown in Tables 3, 4, 5 and 6.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. All blocks are protected at Power Up. In-
structions are provided to protect or unprotect any
block in the application. A second register locks
the protection status while WP is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.
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FPGA/CPLD
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