Low Noise Pseudomorphic HEMT
in a Surface Mount Plastic Package
Technical Data
ATF-33143
Features
• Low Noise Figure
• Excellent Uniformity in
Product Specifications
• Low Cost Surface Mount
Small Plastic Package
SOT-343 (4 lead SC-70)
• Tape-and-Reel Packaging
Option Available
Surface Mount Package
SOT-343
Description
Hewlett Packard’s ATF-33143 is a
high dynamic range, low noise,
PHEMT housed in a 4-lead SC-70
(SOT-343) surface mount plastic
package.
Based on its featured perfor-
mance, ATF-33143 is suitable for
applications in cellular and PCS
base stations, LEO systems,
MMDS, and other systems requir-
ing super low noise figure with
good intercept in the 450 MHz to
10 GHz frequency range.
Other PHEMT devices in this
family are the ATF-34143 and the
ATF-35143. The typical specifica-
tions for these devices at 2 GHz
are shown in the table below:
Pin Connections and
Package Marking
Specifications
• 0.5 dB Noise Figure
• 15 dB Associated Gain
• 22 dBm Output Power at
1 dB Gain Compression
• 33.5 dBm Output 3
rd
Order
Intercept
SOURCE
3Px
Gate Width
1600
µ
800
µ
400
µ
1.9 GHz; 4V, 80 mA (Typ.)
DRAIN
SOURCE
GATE
Note:
Top View. Package marking
provides orientation and identification.
“3P” = Device code
“x” = Date code character. A new
character is assigned for each month, year.
Applications
• Low Noise Amplifier and
Driver Amplifier for
Cellular/PCS Base Stations
• LNA for WLAN, WLL/RLL,
LEO, and MMDS
Applications
• General Purpose Discrete
PHEMT for Other Ultra Low
Noise Applications
Part No.
ATF-33143
ATF-34143
ATF-35143
Bias Point
4 V, 80 mA
4 V, 60 mA
4V, 30 mA
NF (dB) Ga (dB) OIP3 (dBm)
0.5
0.5
0.4
15.0
17.5
18.0
33.5
31.5
28.0
2
ATF-33143 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
DS
P
diss
P
in max
T
CH
T
STG
θ
jc
Parameter
Drain - Source Voltage
[2]
Gate - Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Total Power Dissipation
[4]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[5]
Units
V
V
V
mA
mW
dBm
°C
°C
°C/W
Absolute
Maximum
5.5
-5
-5
I
dss [3]
600
20
160
-65 to 160
145
Notes:
1. Operation of this device above any one
of these parameters may cause
permanent damage.
2. Assumes DC quiesent conditions.
3. V
GS
= 0 V
4. Source lead temperature is 25°C.
Derate 6 mW/°C for T
L
> 60°C.
5. Thermal resistance measured using
150°C Liquid Crystal Measurement
method.
Product Consistency Distribution Charts
[7, 8]
500
+0.6 V
120
6 Sigma=0.30
100
80
Cpk = 1.65937
Std = 0.05
400
I
DS
(mA)
300
0V
-3 Std
60
+3 Std
200
40
100
–0.6 V
20
0
0.2
0
0
2
4
V
DS
(V)
6
8
0.3
0.4
0.5
NF (dB)
0.6
0.7
0.8
Figure 1. Typical I-V Curves
[6]
.
(V
GS
= -0.2 V per step)
100
Cpk = 1.21
Std = 0.94
Figure 2. NF @ 2 GHz, 4 V, 80 mA.
LSL=0.2, Nominal=0.53, USL=0.8
120
100
Cpk = 2.25168
Std = 0.2
80
6 Sigma=1.2
80
60
-3 Std
+3 Std
60
-3 Std
+3 Std
40
40
20
20
0
13
0
29
31
33
OIP3 (dBm)
35
37
14
15
GAIN (dB)
16
17
Figure 3. OIP3 @ 2 GHz, 4 V, 80 mA.
LSL=30.0, Nominal=33.3, USL=37.0
Figure 4. Gain @ 2 GHz, 4 V, 80 mA.
LSL=13.5, Nominal=14.8, USL=
Notes:
6. Under large signal conditions, V
GS
may
swing positive and the drain current may
exceed I
dss
. These conditions are
acceptable as long as the maximum P
diss
and P
in max
ratings are not exceeded.
7. Distribution data sample size is 450
samples taken from 9 different wafers.
Future wafers allocated to this product
may have nominal values anywhere
within the upper and lower spec limits.
8.
Measurements made on production test
board. This circuit represents a trade-off
between an optimal noise match and a
realizeable match based on production test
requirements. Circuit losses have been de-
embedded from actual measurements.
3
ATF-33143 DC Electrical Specifications
T
A
= 25°C, RF parameters measured in a test circuit for a typical device
Symbol
I
dss [1]
V
P [1]
I
d
g
m[1]
I
GDO
I
gss
NF
Parameters and Test Conditions
Saturated Drain Current
Pinchoff Voltage
Quiescent Bias Current
Transconductance
Gate to Drain Leakage Current
Gate Leakage Current
f = 2 GHz
Noise Figure
f = 900 MHz
f = 2 GHz
G
a
Associated Gain
[3]
f = 900 MHz
f = 2 GHz
5 dBm Pout/Tone
f = 900 MHz
5 dBm Pout/Tone
f = 2 GHz
f = 900 MHz
V
DS
= 1.5 V, V
GS
= 0 V
V
DS
= 1.5 V, I
DS
= 10% of I
dss
Units Min. Typ.
[2]
Max.
mA
V
175
-0.65
237
-0.5
100
440
42
0.5
0.5
0.4
0.4
13.5
15
15
21
21
33.5
32
32.5
31
22
21
21
20
305
-0.35
—
—
1000
600
0.8
V
GS
= 0.42 V, V
DS
= 4 V mA
—
V
DS
= 1.5 V, g
m
= I
dss
/V
P
mmho 360
V
GD
= 5 V
V
GD
= V
GS
= -4 V
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
V
DS
= 4 V, I
DS
= 80 mA
V
DS
= 4 V, I
DS
= 60 mA
µA
µA
dB
dB
dB
dB
dBm
dBm
dBm
dBm
30
—
16.5
OIP3
Output 3
rd
Order
Intercept Point
[3]
P
1dB
1 dB Compressed
Compressed Power
[3]
Notes:
1. Guaranteed at wafer probe level.
2. Typical value determined from a sample size of 450 parts from 9 wafers.
3. Measurements obtained using production test board described in Figure 5.
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.5 dB loss)
Input
Matching Circuit
Γ_mag
= 0.20
Γ_ang
= 124°
(0.3 dB loss)
DUT
50 Ohm
Transmission
Line Including
Drain Bias T
(0.5 dB loss)
Output
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P
1dB
, and OIP3 measure-
ments. This circuit represents a trade-off between an optimal noise match and a realizable match based on production test
requirements. Circuit losses have been de-embedded from actual measurements.
4
ATF-33143 Typical Performance Curves
40
40
2V
3V
4V
OIP3, IIP3 (dBm)
20
OIP3, IIP3 (dBm)
2V
3V
4V
30
30
20
10
10
0
0
50
100
150
200
250
I
DSQ
(mA)
0
0
50
100
150
200
250
I
DSQ
(mA)
Figure 6. OIP3, IIP3 vs. Bias
[1]
at
2 GHz.
25
Figure 7. OIP3, IIP3 vs. Bias
[1]
at
900 MHz.
25
20
P
1dB
(dBm)
P
1dB
(dBm)
2V
3V
4V
20
15
15
10
10
5
5
2V
3V
4V
0
0
50
100
150
200
250
I
DSQ
(mA)
0
0
50
100
150
200
250
I
DSQ
(mA)
Figure 8. P
1dB
vs. Bias
[1,2]
at 2 GHz.
Figure 9. P
1dB
vs. Bias
[1,2]
Tuned for NF
@ 4V, 80 mA at 900 MHz.
1.4
1.2
1.0
0.8
0.6
NOISE FIGURE (dB)
16
15
14
G
a
(dB)
22
21
20
G
a
(dB)
1.2
1.0
0.8
0.6
0.4
NF
2V
3V
4V
13
12
NF
19
18
17
16
0
50
100
150
200
I
DSQ
(mA)
11
10
0
50
100
150
200
I
DSQ
(mA)
2V
3V
4V
0.4
0.2
0
250
0.2
250
Figure 10. NF and G
a
vs. Bias
[1]
at
2 GHz.
Figure 11. NF and G
a
vs. Bias
[1]
at
900 MHz.
Notes:
1. Measurements made on a fixed tuned production test board that was tuned for optimal gain match with reasonable noise figure at 4V
80 mA bias. This circuit represents a trade-off between optimal noise match, maximum gain match and a realizable match based on
production test board requirements. Circuit losses have been de-embedded from actual measurements.
2. P
1dB
measurements are performed with passive biasing. Quiescent drain current, I
DSQ
, is set with zero RF drive applied. As P
1dB
is
approached, the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I
DSQ
the device
is running closer to class B as power output approaches P
1dB
. This results in higher P
1dB
and higher PAE (power added efficiency)
when compared to a device that is driven by a constant current source as is typically done with active biasing. As an example, at a V
DS
= 4 V and I
DSQ
= 20 mA, I
d
increases to 62 mA as a P
1dB
of +19 dBm is approached.
NOISE FIGURE (dB)
5
ATF-33143 Typical Performance Curves,
continued
2.0
80 mA
60 mA
30
25
20
80 mA
60 mA
1.5
F
min
(dB)
G
a
(dB)
1.0
15
10
0.5
5
0
0
2
4
6
8
10
FREQUENCY (GHz)
0
0
2
4
6
8
10
FREQUENCY (GHz)
Figure 12. F
min
vs. Frequency and
Current at 4V.
25
25°C
-40°C
85°C
Figure 13. Associated Gain vs.
Frequency and Current at 4V.
2.0
40
25°C
-40°C
85°C
P
1dB
, OIP3 (dBm)
20
G
a
(dB)
1.5
NOISE FIGURE (dB)
35
30
15
1.0
25
10
0.5
20
5
0
5
FREQUENCY (GHz)
10
0
15
0
2000
4000
6000
8000
FREQUENCY (MHz)
Figure 14. F
min
and G
a
vs. Frequency
and Temp at V
DS
= 4V, I
DS
= 80 mA.
35
OIP3, P
1dB
(dBm), GAIN (dB)
Figure 15. P
1dB
, OIP3 vs. Frequency
and Temp at V
DS
= 4V, I
DS
= 80 mA.
35
OIP3, P
1dB
(dBm), GAIN (dB)
3.5
3.0
NOISE FIGURE (dB)
3.5
30
25
20
15
10
5
0
0
50
100
150
200
I
DSQ
(mA)
P
1dB
OIP3
Gain
NF
30
25
20
1.5
15
10
5
0
0
50
100
150
200
I
DSQ
(mA)
P
1dB
OIP3
Gain
NF
2.5
2.0
1.5
1.0
0.5
2.5
0.5
0
250
-0.5
250
Figure 16. OIP3, P
1dB
, NF and Gain vs.
Bias
[1,2]
at 3.9 GHz.
Figure 17. OIP3, P
1dB
, NF and Gain vs.
Bias
[1,2]
at 5.8 GHz.
Notes:
1. Measurements made on a fixed tuned test fixture that was tuned for noise figure at 4V 80 mA bias. This circuit represents a trade-off
between optimal noise match, maximum gain match and a realizable match based on production test requirements. Circuit losses have
been de-embedded from actual measurements.
2. P
1dB
measurements are performed with passive biasing. Quiescent drain current, I
DSQ
, is set with zero RF drive applied. As P
1dB
is
approached, the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I
dsq
the device is
running closer to class B as power output approaches P
1dB
. This results in higher P
1dB
and higher PAE (power added efficiency) when
compared to a device that is driven by a constant current source as is typically done with active biasing. As an example, at a V
DS
= 4 V
and I
DSQ
= 20 mA, I
d
increases to 62 mA as a P
1dB
of +19 dBm is approached.
NOISE FIGURE (dB)
ADI Reference Circuit
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