This specification guarantees that both the high and low trip points of the comparator fall within the 1.20 V to 1.30 V range.
2
The output voltage waveform will exhibit a sawtooth shape due to the comparator hysteresis. The output voltage on the fixed output versions will always be within
the specified range.
3
100 kΩ resistor connected between a 5 V source and the AO pin.
4
All limits at temperature extremes are guaranteed via correlation using standard statistical methods.
Specifications subject to change without notice.
–2–
REV. A
REV. 0
ADP1111
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
SW1 Pin Voltage
SW2 Pin Voltage
Feedback Pin Voltage (ADP1111)
Switch Current
Maximum Power Dissipation
Operating Temperature Range
ADP1111A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
36 V
50 V
−0.5 V to V
IN
5.5 V
1.5 A
500 mW
0°C to 70°C
−65°C to +150°C
300°C
PIN DESCRIPTIONS
Mnemonic
I
LIM
Function
For normal conditions this pin is connected to V
IN
.
When lower current is required, a resistor should be
connected between I
LIM
and V
IN
. Limiting the switch
current to 400 mA is achieved by connecting a 220 Ω
resistor.
Input Voltage.
Collector Node of Power Transistor. For step-down
con-figuration, connect to V
IN
. For step-up configu-
ration, connect to an inductor/diode.
Emitter Node of Power Transistor. For step-down
configuration, connect to inductor/diode. For step-up
configuration, connect to ground. Do not allow this
pin to go more than a diode drop below ground.
Ground.
Auxiliary Gain (GB) Output. The open collector can
sink 300 μA. It can be left open if unused.
Gain Amplifier Input. The amplifier’s positive input is
connected to SET pin and its negative input is con-
nected to the 1.25 V reference. It can be left open if
unused.
On the ADP1111 (adjustable) version this pin is con-
nected to the comparator input. On the ADP1111-3.3,
ADP1111-5 and ADP1111-12, the pin goes directly
to the internal application resistor that sets output
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FPGA/CPLD
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