CCK-L67130V-70 datasheet, PDF - EEWORLD Datasheet

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CCK-L67130V-70: DescriptionDual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, DIP-48; Categorystorage storage; File Size196KB，16 Pages; ManufacturerAtmel (Microchip)

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CCK-L67130V-70 Overview

Dual-Port SRAM, 1KX8, 70ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, DIP-48

CCK-L67130V-70 Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP,
Contacts	48
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
JESD-30 code	R-CDIP-T48
length	61.02 mm
memory density	8192 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Number of functions	1
Number of terminals	48
word count	1024 words
character code	1000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	4.83 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm

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L67130/L67140

1 K

8 CMOS Dual Port RAM 3.3 Volt

Introduction

The L67130/67140 are very low power CMOS dual port

static RAMs organized as 1024

8. They are designed to

be used as a stand-alone 8 bits dual port RAM or as a

combination MASTER/SLAVE dual port for 16 bits or

more width systems. The MHS MASTER/SLAVE dual

port approach in memory system applications results in

full speed, error free operation without the need for

additional discrete logic.

Master and slave devices provide two independent ports

with separate control, address and I/O pins that permit

independent, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the onchip circuitry of

each port in order to enter a very low stand by power

mode.

Using an array of eight transistors (8T) memory cell and

fabricated with the state of the art 1.0

µm

lithography

named SCMOS, the M67130/140 combine an extremely

low standby supply current (typ = 1.0

µA)

with a fast

access time at 45 ns over the full temperature range. All

versions offer battery backup data retention capability

with a typical power consumption at less than 5

µW.

For military/space applications that demand superior

levels of performance and reliability the L67130/67140

is processed according to the methods of the latest

revision of the MIL STD 883 (class B or S) and/or ESA

SCC 9000.

Features

Single 3.3 V

0.3 volt power supply

Fast access time

45 ns(*) to 70 ns

67130L/67140L low power

67130V/67140V very low power

Expandable data bus to 16 bits or more using master/slave

devices when using more than one device.

(*) Preliminary

On chip arbitration logic

BUSY output flag on master

BUSY input flag on slave

INT flag for port to port communication

Fully asynchronous operation from either port

Battery backup operation : 2 V data retention

MATRA MHS

Rev. D (19 Fev. 97)

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