DATA SHEET
128M bits SDRAM
EDS1216AATA, EDS1216CATA
(8M words
×
16 bits)
Description
The EDS1216AATA, EDS1216CATA are 128M bits
SDRAMs organized as 2,097,152 words
×
16 bits
×
4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS1216AATA) and 2.5V
(EDS1216CATA).
They are packaged in 54-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
Features
•
•
•
•
•
3.3V and 2.5V power supply
Clock frequency: 133MHz (max.)
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
•
Burst read/write operation and burst read/single
write operation capability
•
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
•
Programmable /CAS latency (CL): 2, 3
•
Byte control by UDQM and LDQM
•
Refresh cycles: 4096 refresh cycles/64ms
•
2 variations of refresh
Auto refresh
Self refresh
•
TSOP (II) package with lead free solder (Sn-Bi)
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0411E30 (Ver. 3.0)
Date Published July 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2004
EDS1216AATA, EDS1216CATA
Ordering Information
Part number
EDS1216AATA-75-E*
EDS1216AATA-7B-E
EDS1216AATA-75L-E*
EDS1216AATA-7BL-E
EDS1216CATA-75-E*
EDS1216CATA-7B-E
EDS1216CATA-75L-E*
EDS1216CATA-7BL-E*
Supply
voltage
3.3V
Organization
(words
×
bits) Internal Banks
8M
×
16
4
Clock frequency
MHz (max.)
133
/CAS latency
3
Package
54-pin plastic
TSOP (II)
2.5V
8M
×
16
4
133
3
Note: 100MHz operation at /CAS latency = 2.
Part Number
E D S 12 16 A A TA - 75 L - E
Elpida Memory
Type
D: Monolithic Device
Environment Code
E: Lead Free
Power Consumption
Blank: Normal
L: Low Power
Speed
75: 133MHz/CL3
100MHz/CL2
7B: 133MHz/CL3
Product Code
S: SDRAM
Density / Bank
12: 128M/4-bank
Bit Organization
16: x16
Voltage, Interface
A: 3.3V, LVTTL
C: 2.5V, LVTTL
Die Rev.
Package
TA: TSOP (II)
Data Sheet E0411E30 (Ver. 3.0)
2
EDS1216AATA, EDS1216CATA
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................20
Mode Register Configuration.......................................................................................................................21
Power-up sequence.....................................................................................................................................23
Operation of the SDRAM.............................................................................................................................24
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Data Sheet E0411E30 (Ver. 3.0)
3
EDS1216AATA, EDS1216CATA
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
[EDS1216AA]
[EDS1216CA]
Supply voltage relative to VSS
[EDS1216AA]
[EDS1216CA]
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VT
VDD
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to VDD + 0.5 (≤ 4.6 (max.))
–0.5 to VDD + 0.5 (≤ 3.6 (max.))
–0.5 to +4.6
–0.5 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
V
V
mA
W
°C
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
[EDS1216AA]
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
VIL
min.
3.0
0
2.0
–0.3
max.
3.6
0
VDD + 0.3
0.8
Unit
V
V
V
V
Notes
1
2
3
4
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width
≤
5ns).
VIL (min.) = VSS – 1.5V (pulse width
≤
5ns).
[EDS1216CA]
Parameter
Supply voltage
Input high voltage
Input low voltage
Symbol
VDD, VDDQ
VSS, VSSQ
VIH
VIL
min.
2.3
0
1.7
–0.3
max.
2.7
0
VDD + 0.3
0.7
Unit
V
V
V
V
Notes
1
2
3
4
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width
≤
5ns).
VIL (min.) = VSS – 1.5V (pulse width
≤
5ns).
Data Sheet E0411E30 (Ver. 3.0)
4
EDS1216AATA, EDS1216CATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS1216AA]
(TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS1216CA]
EDS1216AA
Parameter
Operating current
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in non
power down
Active standby current in non
power down (input signal
stable)
Burst operating current
Refresh current
Self refresh current
Self refresh current
(L-version)
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
IDD6
IDD6
-XXL
Grade
max.
100
3
2
20
9
4
3
40
25
120
220
1.5
600
EDS1216CA
max.
100
3
2
20
9
4
3
40
25
120
220
1.5
600
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0411E30 (Ver. 3.0)
5
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