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MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers /
Demultiplexers
High−Performance Silicon−Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from V
CC
to V
EE
).
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal−gate MC14051AB, MC14052AB and MC14053AB. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (R
on
) is
more linear over input voltage than R
on
of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
Features
http://onsemi.com
MARKING
DIAGRAMS
16
16
1
PDIP−16
N SUFFIX
CASE 648
MC74HC405xAN
AWLYYWWG
1
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
1
HC405xAG
AWLYWW
16
HC405xA
AWLYWWG
1
16
•
•
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
CC
− V
EE
) = 2.0 to 12.0 V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
Pb−Free Packages are Available*
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
16
HC40
5xA
ALYWG
G
16
1
SOEIAJ−16
F SUFFIX
CASE 966
1
74HC405xA
ALYWG
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 3
Publication Order Number:
MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE − MC74HC4051A
LOGIC DIAGRAM
MC74HC4051A
Single−Pole, 8−Position Plus Common Off
X0
14
X1
15
X2
12
X3
1
X4
5
13
3
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
Select
C
B
A
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
ANALOG
INPUTS/
OUTPUTS
X
MULTIPLEXER/
DEMULTIPLEXER
COMMON
OUTPUT/
INPUT
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
Pinout: MC74HC4051A
(Top View)
V
CC
16
X2
15
X1
14
X0
13
X3
12
A
11
B
10
C
9
1
X4
2
X6
3
X
4
X7
5
X5
6
7
Enable V
EE
8
GND
FUNCTION TABLE − MC74HC4052A
LOGIC DIAGRAM
MC74HC4052A
Double−Pole, 4−Position Plus Common Off
X0
12
14
Control Inputs
Select
Enable
L
L
L
L
H
X = Don’t Care
B
L
L
H
H
X
A
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
ANALOG
INPUTS/OUTPUTS
X1
15
X2
11
X3
Y0
1
5
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
Y1
2
Y2
CHANNEL-SELECT
INPUTS
Y3
10
A
9
B
6
4
Y SWITCH
3
Y
Pinout: MC74HC4052A
(Top View)
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
V
CC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
ENABLE
1
Y0
2
Y2
3
Y
4
Y3
5
Y1
6
7
Enable V
EE
8
GND
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2
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE − MC74HC4053A
LOGIC DIAGRAM
MC74HC4053A
Triple Single−Pole, Double−Position Plus Common Off
X0
13
X1
Y0
1
Y1
Z0
3
Z1
A
10
CHANNEL-SELECT
B
INPUTS
9
C
6
ENABLE
11
5
2
12
14
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
C
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X SWITCH
X
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Z SWITCH
4
Z
X = Don’t Care
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
Pinout: MC74HC4053A
(Top View)
V
CC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
1
Y1
2
Y0
3
Z1
4
Z
5
Z0
6
7
8
GND
Enable V
EE
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎ Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎ Î
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎ Î
Î Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
CC
V
EE
V
IS
V
in
I
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to V
EE
)
– 0.5 to + 7.0
– 0.5 to + 14.0
– 7.0 to + 5.0
V
EE
− 0.5 to
V
CC
+ 0.5
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
– 0.5 to V
CC
+ 0.5
±
25
750
500
450
mA
P
D
Plastic DIP†
EIAJ/SOIC Package†
TSSOP Package†
mW
T
stg
T
L
Storage Temperature Range
– 65 to + 150
260
_C
_C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
MAXIMUM RATINGS
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
3
MC74HC4051A, MC74HC4052A, MC74HC4053A
RECOMMENDED OPERATING CONDITIONS
ÎÎÎ Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎ Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ Î Î
Î
Î
Î Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎ Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎÎ Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î Î
Î
Î
Î
Î Î Î
Î
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
Symbol
V
CC
V
EE
V
IS
V
in
Parameter
Min
2.0
2.0
Max
Unit
V
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to V
EE
)
6.0
12.0
Negative DC Supply Voltage, Output (Referenced to
GND)
Analog Input Voltage
− 6.0
V
EE
GND
V
CC
V
CC
1.2
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
GND
V
IO
*
T
A
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Channel Select or Enable Inputs)
– 55
0
0
0
0
+ 125
1000
600
500
400
_C
ns
t
r
, t
f
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
*For voltage drops across switch greater than 1.2V (switch on), excessive V
CC
current may be
drawn; i.e., the current out of the switch may contain both V
CC
and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND) V
EE
= GND, Except Where Noted
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Condition
R
on
= Per Spec
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
0.1
≤85°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
≤125°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
Unit
V
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
R
on
= Per Spec
V
I
in
I
CC
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND,
V
EE
= − 6.0 V
Channel Select, Enable and
V
IS
= V
CC
or GND;
V
EE
= GND
V
IO
= 0 V
V
EE
= − 6.0
mA
mA
6.0
6.0
1
4
10
40
20
80
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
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