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DS1250Y/AB
4096k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 512k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full
±10%
V
CC
operating range (DS1250Y)
Optional
±5%
V
CC
operating range
(DS1250AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 32-pin DIP package
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PCM allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
A15
A16
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND V
BAT
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0 - A18
DQ0 - DQ7
CE
WE
OE
V
CC
GND
NC
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
- No Connect
1 of 12
121907
DS1250Y/AB
DESCRIPTION
The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250 devices can be used in place of existing 512k x
8 static RAMs directly conforming to the popular byte-wide 32-pin DIP standard. DS1250 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1250 executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip Enable)
and
OE
(Output Enable) are active (low). The unique address specified by the 19 address inputs (A
0
-
A
18
) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eight
data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not satisfied,
then data access must be measured from the later-occurring signal (
CE
or
OE
) and the limiting parameter
is either t
CO
for
CE
or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1250 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1250AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1250Y provides full functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1250AB and 4.5 volts for the
DS1250Y.
FRESHNESS SEAL
Each DS1250 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than 4.25 volts, the lithium
energy source is enabled for battery back-up operation.
2 of 12
DS1250Y/AB
PACKAGES
The DS1250 is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin
DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1250 PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
temperature reflow soldering. After a DS1250 PCM module base is reflow soldered, a DS9034PC
PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC
is keyed to prevent improper attachment. DS1250 module bases and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
DIP Module
Caution: Do Not Reflow
PowerCap Module
*
-0.3V to +6.0V
0°C to 70°C, -40°C to +85°C for IND parts
-40°C to +70°C, -40°C to +85°C for IND parts
+260°C for 10 seconds
(Wave or Hand Solder Only)
See IPC/JEDEC J-STD-020
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
DS1250AB Power Supply Voltage
DS1250Y Power Supply Voltage
Logic 1
Logic 0
SYMBOL
V
CC
V
CC
V
IH
V
IL
MIN
4.75
4.5
2.2
0.0
TYP
5.0
5.0
MAX
5.25
5.5
V
CC
+0.8
(t
A
: See Note 10)
UNITS
V
V
V
V
NOTES
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
≥
V
IH
≤
V
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current
CE
=2.2V
Standby Current
CE
=V
CC
-0.5V
Operating Current
Write Protection Voltage (DS1250AB)
Write Protection Voltage (DS1250Y)
(V
CC
=5V
±
5% for DS1250AB)
(t
A
: See Note 10) (V
CC
=5V
±
10% for DS1250Y)
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO1
V
TP
V
TP
3 of 12
MIN
-1.0
-1.0
-1.0
2.0
TYP
MAX
+1.0
+1.0
UNITS
μA
μA
mA
mA
NOTES
200
50
4.50
4.25
4.62
4.37
600
150
85
4.75
4.5
μA
μA
mA
V
V
DS1250Y/AB
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
5
5
MAX
10
10
pF
pF
(t
A
=25°C)
UNITS
NOTES
AC ELECTRICAL
CHARACTERISTICS
(V
CC
=5V
±
5% for DS1250AB)
(t
A
: See Note 10) (V
CC
=5V
±
10% for DS1250Y)
DS1250AB-70
DS1250Y-70
DS1250AB-100
DS1250Y-100
PARAMETER
Read Cycle Time
Access Time
OE
CE
OE
SYMBOL
t
RC
t
ACC
t
OE
t
CO
t
COE
t
OD
t
OH
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
MIN
70
MAX
70
35
70
MIN
100
MAX
100
50
100
UNITS
ns
ns
ns
ns
ns
NOTES
to Output Valid
to Output Valid
or
CE
to Output Active
5
25
5
70
55
0
5
15
25
5
30
0
10
5
35
5
100
75
0
5
15
35
5
40
0
10
5
5
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Z from
WE
Output Active from
WE
Data Setup Time
Data Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
12
13
5
5
4
12
13
4 of 12
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