M16C/29 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0072-0030Z
Rev.0.30
2004.06.15
1. Overview
The M16C/29 group of single-chip microcomputers is built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
They also contain a CAN module, makes it suitable for control of cars and LAN system of FA. In addition,
they contain a multiplier and a DMAC, also making it suitable for control of various OA, communication, and
industrial equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
Automotive body, safety & audio, LAN system of FA, etc.
------Table of Contents------
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.30 2004.06.15
REJ03B0072-0030Z
page 1 of 30
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/29 group 80-pin device.
Table 1.2.2 lists performance outline of M16C/29 group 64-pin device.
Table 1.2.1. Performance outline of M16C/29 group (80-pin device)
Item
Performance
CPU
Number of basic instructions 91 instructions
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 3.0V to 5.5V)
(Normal-ver./T-ver.)
Shortest instruction
excution time
100 ns (f(BCLK)= 10MH
Z
, V
CC
= 2.7V to 5.5V)
(Normal-ver.)
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 4.2V to 5.5V -40 to 105°C) (V-ver.)
62.5 ns (f(BCLK)= 16MH
Z
, V
CC
= 4.2V to 5.5V -40 to 125°C) (V-ver.)
Operation mode
Single chip mode
Address space
1M bytes
Memory capacity
ROM/RAM : See the product list
Peripheral
port
Input/Output : 71 lines
function
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I
2
C bus
1
, or IEbus
2
2 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I
2
C bus
1
)
A/D converter
10 bits x 27 channels
DMAC
2 channels
CRC calcuration circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
CAN module
1 channel 2.0B BOSCH compliant
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
28 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
(These circuits contain a built-in feedback
• Main clock
½
• Sub-clock
resistor and external ceramic/quartz oscillator)
• On-chip oscillator(main-clock oscillation stop detect function)
• PLL frequency synthesizer
Low voltage detection circuit Available (Normal-ver.) Not available (T-ver./V-ver.)
Electrical
Power supply voltage
V
CC
=3.0V to 5.5V (f(BCLK)=20MH
Z
)
(Normal-ver.)
Characteristics
V
CC
=2.7V to 5.5V (f(BCLK)=10MH
Z
)
V
CC
=3.0V to 5.5V
(T-ver.)
V
CC
=4.2V to 5.5V
(V-ver.)
Power consumption
18mA (V
CC
=5V, f(BCLK)=20MHz)
25
µA
(V
CC
=5V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8
µA
(V
CC
=5V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.8
µA
(V
CC
=5V, when stop mode)
Flash memory Program/erase voltage
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
Number of program/erase
100 times ( Block A ,Block B : 10,000 times (option
3
) )
Operating ambient temperature
-20 to 85°C / -40 to 85°C (option
3
)
(Normal-ver.)
-40 to 85°C (T-ver.)
-40 to 125°C (V-ver.)
Package
80-pin plastic mold QFP
Notes:
1. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
Rev.0.30 2004.06.15
REJ03B0072-0030Z
page 2 of 30
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Table 1.2.2. Performance outline of M16C/29 group (64-pin device)
Item
Performance
CPU
Number of basic instructions 91 instructions
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 3.0V to 5.5V)
(Normal-ver./T-ver.)
Shortest instruction
excution time
100 ns (f(BCLK)= 10MH
Z
, V
CC
= 2.7V to 5.5V)
(Normal-ver.)
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 4.2V to 5.5V -40 to 105°C) (V-ver.)
62.5 ns (f(BCLK)= 16MH
Z
, V
CC
= 4.2V to 5.5V -40 to 125°C) (V-ver.)
Operation mode
Single chip mode
Address space
1M bytes
Memory capacity
ROM/RAM : See the product list
Peripheral
port
Input/Output : 55 lines
function
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I
2
C bus
1
, or IEbus
2
1 channel (SI/O3)
Clock synchronous
1 channel (Multi-Master I
2
C bus
1
)
A/D converter
10 bits x 16 channels
DMAC
2 channels
CRC calcuration circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
CAN module
1 channel 2.0B BOSCH compliant
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
28 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
(These circuits contain a built-in feedback
• Main clock
½
• Sub-clock
resistor and external ceramic/quartz oscillator)
• On-chip oscillator(main-clock oscillation stop detect function)
• PLL frequency synthesizer
Low voltage detection circuit Available (Normal-ver.) Not available (T-ver./V-ver.)
Electrical
Power supply voltage
V
CC
=3.0V to 5.5V (f(BCLK)=20MH
Z
)
(Normal-ver.)
Characteristics
V
CC
=2.7V to 5.5V (f(BCLK)=10MH
Z
)
V
CC
=3.0V to 5.5V
(T-ver.)
V
CC
=4.2V to 5.5V
(V-ver.)
Power consumption
18mA (V
CC
=5V, f(BCLK)=20MHz)
25
µA
(V
CC
=5V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8
µA
(V
CC
=5V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.8
µA
(V
CC
=5V, when stop mode)
Flash memory Program/erase voltage
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
Number of program/erase
100 times ( Block A ,Block B : 10,000 times (option
3
) )
Operating ambient temperature
-20 to 85°C / -40 to 85°C (option
3
)
(Normal-ver.)
-40 to 85°C (T-ver.)
-40 to 125°C (V-ver.)
Package
64-pin plastic mold QFP
Notes:
1. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
Rev.0.30 2004.06.15
REJ03B0072-0030Z
page 3 of 30
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/29 group, 80-pin device.
8
8
8
8
8
8
8
7
8
I/O
Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
3-phase PWM
Timer S
Input Capture (8 channels)
Output Compare (8 channels)
A/D converter
(10bits x 27 channels)
DMAC (2 channels)
CRC arithmetic circuit
(CCITT,CRC-16)
Serial Ports
U(S)ART/SIO (channel 0)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C bus/IEBus
(channel 2)
SIO (channel 3)
SIO (channel 4)
Multi-master I
2
C bus
CAN module
(1 channel)
System Clock Generator
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
On-chip Oscillator
Watchdog Timer
Low voltage detect
M16C/60 series 16-bit CPU Core
Program Counter
Registers
R0H
R0H
R1H
R1H
R2
R2
R3
R3
A0
A0
A1
A1
FR
FB
SB
R0L
R0L
R1L
R1L
PC
Stack Pointers
ISP
USP
Vector Table
INTB
Flag Register
FLG
Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
Rev.0.30 2004.06.15
REJ03B0072-0030Z
page 4 of 30
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/29 Group
1. Overview
Figure 1.3.2 is a block diagram of the M16C/29 group, 64-pin device.
4
3
8
4
8
8
8
4
8
I/O
Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
3-phase PWM
Timer S
Input Capture (8 channels)
Output Compare (8 channels)
A/D converter
(10bits x 16 channels)
DMAC (2 channels)
Low voltage detect
Serial Ports
U(S)ART/SIO (channel 0)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C bus/IEBus
(channel 2)
SIO (channel 3)
Multi-master I
2
C bus
System Clock Generator
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
On-chip Oscillator
Watchdog Timer
CRC arithmetic circuit
(CCITT,CRC-16)
CAN module
(1 channel)
M16C/60 series 16-bit CPU Core
Program Counter
Registers
R0H
R0H
R1H
R1H
R2
R2
R3
R3
A0
A0
A1
A1
FR
FB
SB
R0L
R0L
R1L
R1L
PC
Stack Pointers
ISP
USP
Vector Table
INTB
Flag Register
FLG
Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
Rev.0.30 2004.06.15
REJ03B0072-0030Z
page 5 of 30
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