Latch-up Current..................................................... > 200 mA
Operating Range
Product
CY62148DV30L
CY62148DV30LL
CY62148DV30LL Automotive-A –40°C to +85°C
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
[7]
2.2V to
3.6V
Electrical Characteristics
Over the Operating Range
55 ns
Parameter
V
OH
V
OL
V
IH
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
Test Conditions
V
CC
= 2.20V
V
CC
= 2.70V
V
CC
= 2.20V
V
CC
= 2.70V
1.8
2.2
–0.3
–0.3
–1
–1
Ind’l
Ind’l
Ind’l
Ind’l
I
SB1
Automatic CE
Power-down
Current —
CMOS Inputs
Automatic CE
Power-down
Current —
CMOS Inputs
CE > V
CC
−0.2V,
V
IN
>V
CC
–0.2V, V
IN
<0.2V)
f = f
max
(Address and Data Only),
f = 0 (OE, and WE), V
CC
=3.60V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
Ind’l
Ind’l
L
LL
L
LL
L
LL
8
8
1.5
1.5
2
2
Min Typ
[4]
Max
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
15
10
3
3
12
8
2
2
2
2
12
8
2
2
8
8
8
8
µA
1.5
1.5
3
3
8
8
10
10
1.8
2.2
–0.3
–0.3
–1
–1
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
70 ns
Min Typ
[4]
Max
Unit
V
V
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
µA
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IX
I
OZ
I
CC
Input LOW
Voltage
Input Leakage
Current
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
Output Leakage GND < V
O
< V
CC
, Output Disabled
Current
V
CC
Operating
Supply Current
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
f = 1 MHz
Auto-A LL
Auto-A LL
Auto-A LL
Ind’l
Ind’l
L
LL
I
SB2
Auto-A LL
Notes:
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100
µs
ramp time from 0 to V
CC(min)
and 200
µs
wait time after V
CC
stabilization.
Document #: 38-05341 Rev. *D
Page 3 of 10
CY62148DV30
Capacitance
(for all packages)
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5
inch, four-layer printed circuit
board
VFBGA
72
8.86
TSOP II
75.13
8.95
SOIC
55
22
Unit
°C/W
°C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
GND
10%
ALL INPUT PULSES
90%
90%
10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
TH
OUTPUT
Parameters
R1
R2
R
TH
V
TH
2.5V (2.2V – 2.7V)
16667
15385
8000
1.20
3.0V (2.7V – 3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[8]
t
R[9]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 1.5V, CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
Ind’l
L
0
t
RC
Ind’l/Auto-A LL
Conditions
Min Typ
[4]
Max
1.5
9
6
Unit
V
µA
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
µs
or stable at V
CC(min)
>
100
µs.
1.5V
t
CDR
V
DR
> 1.5 V
1.5V
t
R
Document #: 38-05341 Rev. *D
Page 4 of 10
CY62148DV30
Switching Characteristics
(Over the Operating Range)
[10]
55 ns
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[13]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[11, 12]
WE HIGH to Low Z
[11]
10
55
40
40
0
0
40
25
0
20
10
70
45
45
0
0
45
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[11]
OE HIGH to High Z
[11,12]
CE LOW to Low Z
[11]
CE HIGH to High Z
[11, 12]
CE LOW to Power-up
CE HIGH to Power-up
0
55
10
20
0
70
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min
Max
Min
70 ns
Max
Unit
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes:
10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the
“AC Test Loads and Waveforms” on page 4.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
12. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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