DATASHEET
VIDEO GENLOCK PLL
Description
The ICS9173B provide the analog PLL circuit blocks to
implement a frequency multiplier. Because the device is
configured to use an external divider in the PLL clock
feedback path, a large divider can be used to result in a
large frequency multiplication ratio. This is useful when
using a low frequency input clock to generate a high
frequency output clock. The ICS9173B contains a phase
detector, charge pump, loop filter, and voltage-controlled
oscillator (VCO). The ICS674-01 can be used as the
external feedback divider.
A common application of the ICS9173B is the
implementation of a video genlock circuit. Because of this,
the ICS9173B inputs operate on the negative-going clock
edge.
The ICS9173B is pin and function compatible to the
AV9173-01/15.
ICS9173B
Features
•
Phase-detector/VCO circuit block
•
Ideal for genlock system
•
Reference clock range 12 kHz to 1 MHz for full output
clock range
•
Output clock range of 1.25 to 75 MHz (-01), and 0.625 to
37.5 MHz (-15). See “Allowable Input Frequency to
Output Frequency” table for conditions
•
•
•
•
On-chip loop filter
Single 5 V power supply
Low power CMOS technology
8-pin SOIC package
Block Diagram
IDT®
VIDEO GENLOCK PLL
1
ICS9173B
REV D 012913
ICS9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Pin Assignment
FBIN
IN
GND
FS0
1
2
3
4
8 pin SOIC
8
7
6
5
CLK2
VDD
CLK1
OE
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
Pin Name
FBIN
IN
GND
FS0
OE
CLK1
VDD
CLK2
Pin Type
Input
Input
Power
Input
Input
Output
Power
Output
Feedback input.
Pin Description
Input for reference sync pulse.
Ground.
Frequency select 0 input.
Output enable.
Clock output 1.
Power supply (+5 V).
Clock output 2 (divided-by-2 from Clock 1).
Allowable Input Frequency to Output Frequency for ICS9173B-01 (in MHz)
(ICS9173B-15 outputs run at exactly half of the ICS9173B-01 frequencies)
f
OUT
for FS = 0
f
IN
(kHz)
12 < f
IN
< 14 kHz
14 < f
IN
< 17 kHz
17 < f
IN
< 30 kHz
30 < f
IN
< 35 kHz
35 < f
IN
< 1000 kHz
CLK1 Output
44.0 to 75
30.0 to 75
25.0 to 75
15.0 to 75
10.0 to 75
CLK2 Output
22.0 to 37.5
15.0 to 37.5
12.5 to 37.5
7.5 to 37.5
5.0 to 37.5
f
OUT
for FS = 1
CLK1 Output
11.0 to 18.75
7.5 to 18.75
6.25 to 18.75
3.75 to 18.75
2.5 to 18.75
CLK2 Output
5.5 to 9.375
3.75 to 9.375
3.125 to 9.375
1.875 to 9.375
1.25 to 9.375
IDT®
VIDEO GENLOCK PLL
2
ICS9173B
REV D 012913
ICS9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Using the ICS9173B in Genlock Applications
Most video sources, such as video cameras, are
asynchronous, free-running devices. To digitize video or
synchronize one video source to another free-running
reference video source, a video “genlock” (generator lock)
circuit is required. The ICS9173B integrates the analog
blocks which make the task much easier.
In the complete video genlock circuit, the primary function of
the ICS9173B is to provide the analog circuitry required to
generate the video dot clock within a PLL. This application
is illustrated in Figure 1. The input reference signal for this
circuit is the horizontal synchronization (H-SYNC) signal. If
a composite video reference source is being used, the
h-sync pulses must be separated from the composite signal.
A video sync separator circuit, such as the National
Semiconductor LM1881, can be used for this purpose.
The clock feedback divider shown in Figure 1 is a digital
divider used within the PLL to multiply the reference
frequency. Its divide ratio establishes how many video dot
clock cycles occur per h-sync pulse. For example, if 880
pixel clocks are desired per h-sync pulse, then the divider
ratio is set to 880. Hence, together the h-sync frequency and
external divider ratio establish the dot clock frequency:
f
OUT
= f
IN
x N where N is external divide ratio
Both input pins IN and FBIN respond only to negative-going
clock edges of the input signal. The H-SYNC signal must be
constant frequency in the 12 kHz to 1 MHz range and stable
(low clock jitter) for creation of a stable output clock.
The output hook-ups of the ICS9173B are dictated by the
desired dot clock frequency. The primary consideration is
the internal VCO which operates over a frequency range of
10 MHz to 75 MHz. Because of the selectable VCO output
divider and the additional divider on output CLK2, four
distinct output frequency ranges can be achieved. The
following Table lists these ranges and the corresponding
device configuration.
FS0
State
0
0
1
1
Output
Used
CLK1
CLK2
CLK1
CLK2
Frequency/Range
ICS9173B-01
10 to 75 MHz
5 to 37.5 MHz
2.5 to 18.75 MHz
1.25 to 9.375 MHz
Frequency/Range
IcS9173B-15
5 to 37.5 MHz
2.5 to 18.75 MHz
1.25 to 9.375 MHz
0.625 to 4.6875 MHz
Note that both outputs, CLK1 and CLK2, are available
during operation even though only one is fed back via the
external clock divider.
Pin 5, OE, tristates both CLK1 and CLK2 upon logic low
input. This feature can be used to revert dot clock control to
the system clock when not in genlock mode (hence, when in
genlock mode the system dot clock must be tristated).
When unused, inputs FS0 and OE must be tied to either
GND (logic low) or VDD (logic high).
Figure 1: Typical Application of ICS9173B in a Video Genlock System
IDT®
VIDEO GENLOCK PLL
3
ICS9173B
REV D 012913
ICS9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS9173B. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
Storage Temperature
Voltage on I/O Pins referenced to GND
Junction Temperature
Soldering Temperature
Power Dissipation
7V
-65 to +150C
Rating
GND - 0.5 V to VDD + 0.5 V
125C
260C
0.5 Watts
Recommended Operation Conditions
Parameter
Operating Temperature under Bias
Power Supply Voltage (measured with respect to
GND)
Min.
-0
+4.75
Typ.
+5 V
Max.
+70
+5.25
Units
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 5 V ±5%,
Ambient Temperature 0 to +70C
Parameter
Operating Supply Current
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
1
Output High Voltage
1
Output High Voltage
1
Symbol
IDD
V
IH
V
IL
I
IL
I
IH
V
OL
V
OH1
V
OH2
V
OH3
Conditions
No load,50 MHz
VDD = 5 V
VDD = 5 V
VIN = 0V
VIN = VDD
I
OL
= 8 mA
I
OH
= -1 mA
I
OH
= -4 mA
I
OH
= -8 mA
Min.
Typ.
20
Max.
50
0.8
Units
mA
V
V
µA
2.0
-5
-5
VDD-0.4
VDD-0.8
2.4
5
0.4
µA
V
V
V
V
Notes:
1. Duty cycle measured at 1.4 V.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical
pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
IDT®
VIDEO GENLOCK PLL
4
ICS9173B
REV D 012913
ICS9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 5 V ±5%,
Ambient Temperature 0 to +70 C
Parameter
Output Clock Rise Time
1
Output Clock Fall Time
1
Output Rise Time
1
Output Rise Time
1
Output Fall Time
1
Output Fall Time
1
Output Duty Cycle
1
One-Sigma Jitter
1, 5
Jitter, Absolute
1, 5
One-Sigma Jitter
1, 5
Jitter, Absolute
1, 5
Line-to-Line Jitter
1
, Absolute
2
Input Frequency
1
, IN or FBIN
CLK1 Frequency, -01
1, 3, 4
Symbol
ICLK
r
ICLK
f
t
r1
t
r2
t
f1
t
f2
T1
S
1
T
ABS
1
T1
S
2
T
ABS
2
T
LABS
f
IN
f
CLK1
Conditions
Min.
Typ.
Max. Units
10
10
ns
ns
ns
ns
ns
ns
%
ps
ps
%
%
ns
1000
75
75
75
75
75
37.5
37.5
37.5
37.5
37.5
MHz
kHz
MHz
15 pF load, 0.8 to 2.0V
15 pF load, 20% to 80% VDD
15 pF load, 0.8 to 2.0V
15 pF load, 80% to 20% VDD
15 pF load
CLK1 frequency
3
, 25 MHz
CLK1 frequency
3
, 25 MHz
CLK1 frequency < 25 MHz
CLK1 frequency < 25 MHz
-400
40
0.6
1.3
0.6
0.7
47
120
±250
1.5
3.0
1.5
2.0
55
250
400
1
2
±4
see allowable fi below
12 < f
IN
< 14 kHz
14 < f
IN
< 17 kHz
17 < f
IN
< 30 kHz
30 < f
IN
< 35 kHz
35 < f
IN
< 1000 kHz
12
44
30
25
15
10
22
15
12.5
7.5
5
CLK1 Frequency, -15
1, 3, 4
f
CLK1
12 < f
IN
< 14 kHz
14 < f
IN
< 17 kHz
17 < f
IN
< 30 kHz
30 < f
IN
< 35 kHz
35 < f
IN
< 1000 kHz
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical
pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides
guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following
these guidelines, the ICS9173B will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot
variation.
5. Jitter values are measured at frequencies > 25 MHz for IDT9173B-01, for ICS9173B-15, jitter is measured at
frequency > 12.5 MHz.
IDT®
VIDEO GENLOCK PLL
5
ICS9173B
REV D 012913
京公网安备 11010802033920号
EEWORLD
