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BU-61705F3-500Q

Description
Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, CERAMIC, QFP-72
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size577KB,54 Pages
ManufacturerData Device Corporation
Download Datasheet Parametric View All

BU-61705F3-500Q Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, CERAMIC, QFP-72

BU-61705F3-500Q Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerData Device Corporation
Parts packaging codeQFP
package instructionQFF,
Contacts72
Reach Compliance Codecompliant
Address bus width5
boundary scanNO
maximum clock frequency20 MHz
letter of agreementMIL-STD-1553A; MIL-STD-1553B; STANAG-3838
Data encoding/decoding methodsBIPH-LEVEL(MANCHESTER)
Maximum data transfer rate0.125 MBps
External data bus width16
JESD-30 codeS-CQFP-F72
JESD-609 codee0
length25.4 mm
low power modeNO
Number of serial I/Os2
Number of terminals72
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQFF
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.94 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width25.4 mm
uPs/uCs/peripheral integrated circuit typeSERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
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BU-61703/61705
Simple System RT (SSRT)
FEATURES
Complete Integrated Remote
Terminal Including:
Dual Low-Power 5V Only Transceiver
Complete RT Protocol Logic
Supports MIL-STD-1553A/B Notice 2,
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
1.0 X 1.0 Inch, 72-pin Package
Choice of 5V or 3.3V Logic Power
Meets 1553A/McAir Response Time
Requirements
Internal FIFO for Burst Mode
Capability on Receive Data
DESCRIPTION
The BU-61703/5 Simple System RT (SSRT) MIL-STD-1553 terminals
provide a complete interface between a simple system and a MIL-
STD-1553 bus. These terminals integrate dual transceiver, protocol
logic, and a FIFO memory for received messages in a 1.0 inch square
ceramic package. The SSRT provides multi-protocol support of MIL-
STD-1553A/B, MIL-STD-1760, McAir, and STANAG-3838.
The SSRT's transceivers are completely monolithic, require only a
+5V supply, and consume low power. There are versions of the sim-
ple system RT available with transceivers trimmed for MIL-STD-1760
compliance, or compatible to McAir standards. As a means of further
reducing power consumption, the SSRT is available in versions with
its logic powered by +3.3V, or +5V. The SSRT can operate with a
choice of clock frequencies of 10, 12, 16, or 20 MHz.
The SSRT incorporates a built-in self-test (BIT). This BIT, which is
processed following power turn-on or after receipt of an Initiate self-
test mode command, provides a comprehensive test of the SSRT's
encoders, decoders, protocol, transmitter watchdog timer, and proto-
col. The SSRT also includes an auto-configuration feature.
The SSRT is ideal for stores and other simple systems that do not
require a microprocessor. To streamline the interface to simple sys-
tems, the SSRT includes an internal 32-word FIFO for received data
words. This serves to ensure that only complete, consistent blocks of
validated data words are transferred to a system.
16-bit DMA Interface
Auto Configuration Capability
Comprehensive Built-In Self-Test
Direct Interface to Simple
(Processorless) Systems
Selectable Input Clock:
10, 12, 16, or 20 MHz
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7234
©
2000 Data Device Corporation
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