PD - 94520
AUTOMOTIVE MOSFET
Benefits
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IRF1302S
IRF1302L
HEXFET
®
Power MOSFET
D
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
G
V
DSS
= 20V
R
DS(on)
= 4.0mΩ
S
I
D
= 174A
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET
®
Power MOSFET utilizes the lastest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive avalanche
rating. These benefits combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety
of other applications.
D
2
Pak
IRF1302S
TO-262
IRF1302L
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
174
120
700
200
1.4
± 20
350
See Fig.12a, 12b, 15, 16
TBD
-55 to + 175
300 (1.6mm from case )
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient (PCB mount)
Typ.
–––
–––
Max.
0.74
40
Units
°C/W
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1
07/16/02
IRF1302S/IRF1302L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
oss
C
oss
C
oss
eff.
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
20
–––
–––
2.0
59
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.021
3.3
–––
–––
–––
–––
–––
–––
79
18
31
28
130
47
16
4.5
7.5
3600
2370
520
5710
2370
3540
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
4.0
mΩ V
GS
= 10V, I
D
= 104A
4.0
V
V
DS
= 10V, I
D
= 250µA
–––
S
V
DS
= 15V, I
D
= 104A
20
V
DS
= 20V, V
GS
= 0V
µA
250
V
DS
= 16V, V
GS
= 0V, T
J
= 150°C
200
V
GS
= 20V
nA
-200
V
GS
= -20V
120
I
D
= 104A
27
nC V
DS
= 16V
46
V
GS
= 10V
–––
V
DD
= 11V
–––
I
D
= 104A
ns
–––
R
G
= 4.5Ω
–––
V
GS
= 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
V
GS
= 0V
–––
pF
V
DS
= 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
–––
V
GS
= 0V, V
DS
= 16V, ƒ = 1.0MHz
–––
V
GS
= 0V, V
DS
= 0V to 16V
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 174
showing the
A
G
integral reverse
––– ––– 700
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 104A, V
GS
= 0V
––– 66 100
ns
T
J
= 25°C, I
F
= 104A
––– 130 200
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
2
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IRF1302S/IRF1302L
10000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
10000
ID, Drain-to-Source Current (A)
1000
ID, Drain-to-Source Current (A)
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
100
4.5V
10
10
4.5V
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000.00
2.0
I
D
= 174A
ID, Drain-to-Source Current
(Α
)
T J = 175°C
R
DS(on)
, Drain-to-Source On Resistance
1.5
100.00
(Normalized)
1.0
0.5
T J = 25°C
VDS = 15V
10.00
4.0
5.0
20µs PULSE WIDTH
6.0
7.0
V
GS
= 10V
0.0
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T
J
, Junction Temperature
(
°
C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRF1302S/IRF1302L
100000
12
VGS = 0V,
f = 1 MHZ
Ciss = C + Cgd, C
gs
ds SHORTED
Crss = C
gd
Coss = C + Cgd
ds
V
GS
, Gate-to-Source Voltage (V)
I
D
=
104A
V
DS
= 16V
10
C, Capacitance(pF)
10000
7
Ciss
Coss
1000
5
Crss
2
100
1
10
100
0
0
20
40
60
80
100
VDS, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
T
J
= 175
°
C
ID , Drain-to-Source Current (A)
1000
I
SD
, Reverse Drain Current (A)
10
100
100µsec
1msec
T
J
= 25
1
°
C
10
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10
10msec
V
GS
= 0 V
0.1
0.2
0.7
1.2
1.7
2.2
V
SD
,Source-to-Drain Voltage (V)
100
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRF1302S/IRF1302L
175
LIMITED BY PACKAGE
V
DS
V
GS
R
D
131
R
G
10V
D.U.T.
+
I
D
, Drain Current (A)
-
V
DD
88
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
44
V
DS
90%
0
25
50
75
100
125
150
175
T
C
, Case Temperature
( ° C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
1
(Z
thJC
)
D = 0.50
0.20
Thermal Response
0.1
0.10
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D =
2. Peak T
t
1
/ t
2
+T
C
1
0.05
0.02
0.01
J
= P
DM
x Z
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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