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TC74VHC20F

Description
Dual 4-Input NAND Gate
Categorylogic    logic   
File Size207KB,9 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

TC74VHC20F Overview

Dual 4-Input NAND Gate

TC74VHC20F Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerToshiba Semiconductor
Parts packaging codeSOIC
package instructionSOP, SOP14,.3
Contacts14
Reach Compliance Codeunknow
seriesAHC/VHC
JESD-30 codeR-PDSO-G14
length10.3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2/5.5 V
Prop。Delay @ Nom-Su8 ns
propagation delay (tpd)11.5 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.9 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width5.3 mm
Base Number Matches1
TC74VHC20F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC20F,TC74VHC20FN,TC74VHC20FT,TC74VHC20FK
Dual 4-Input NAND Gate
The TC74VHC20 is an advanced high speed CMOS 4-INPUT
NAND GATE fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 3 stages including a buffer
output, which provide high noise immunity and stable output.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHC20F
TC74VHC20FN
Features
High speed: t
pd
=
3.3 ns (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
2
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Power down protection is provided on all inputs.
Balanced propagation delays: t
pLH
t
pHL
Wide operating voltage range: V
CC
(opr)
=
2 to 5.5 V
Pin and function compatible with 74ALS20
TC74VHC20FT
TC74VHC20FK
Weight
SOP14-P-300-1.27A
SOL14-P-150-1.27
TSSOP14-P-0044-0.65A
VSSOP14-P-0030-0.50
: 0.18 g (typ.)
: 0.12 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1
2008-05-01

TC74VHC20F Related Products

TC74VHC20F TC74VHC20FT TC74VHC20FK TC74VHC20FN TC74VHC20F_08
Description Dual 4-Input NAND Gate Dual 4-Input NAND Gate Dual 4-Input NAND Gate Dual 4-Input NAND Gate Dual 4-Input NAND Gate
Is it lead-free? Lead free Lead free - Lead free -
Is it Rohs certified? conform to conform to - incompatible -
Maker Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor -
Parts packaging code SOIC TSSOP SSOP SOIC -
package instruction SOP, SOP14,.3 TSSOP, TSSOP14,.25 VSSOP, SOP, SOP14,.25 -
Contacts 14 14 14 14 -
Reach Compliance Code unknow unknow unknow unknow -
series AHC/VHC AHC/VHC AHC/VHC/H/U/V AHC/VHC -
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 -
length 10.3 mm 5 mm 4 mm 8.65 mm -
Load capacitance (CL) 50 pF 50 pF - 50 pF -
Logic integrated circuit type NAND GATE NAND GATE NAND GATE NAND GATE -
MaximumI(ol) 0.008 A 0.008 A - 0.008 A -
Number of functions 2 2 2 2 -
Number of entries 4 4 4 4 -
Number of terminals 14 14 14 14 -
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C -
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code SOP TSSOP VSSOP SOP -
Encapsulate equivalent code SOP14,.3 TSSOP14,.25 - SOP14,.25 -
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR -
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH SMALL OUTLINE -
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED -
power supply 2/5.5 V 2/5.5 V - 2/5.5 V -
Prop。Delay @ Nom-Su 8 ns 8 ns - 8 ns -
propagation delay (tpd) 11.5 ns 11.5 ns 11.5 ns 11.5 ns -
Certification status Not Qualified Not Qualified Not Qualified Not Qualified -
Schmitt trigger NO NO - NO -
Maximum seat height 1.9 mm 1.2 mm 1 mm 1.75 mm -
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V -
Minimum supply voltage (Vsup) 2 V 2 V 2 V 2 V -
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V -
surface mount YES YES YES YES -
technology CMOS CMOS CMOS CMOS -
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL -
Terminal form GULL WING GULL WING GULL WING GULL WING -
Terminal pitch 1.27 mm 0.65 mm 0.5 mm 1.27 mm -
Terminal location DUAL DUAL DUAL DUAL -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED -
width 5.3 mm 4.4 mm 3 mm 3.9 mm -
Base Number Matches 1 1 1 1 -
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