Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
1
1.1
FEATURES
General
UDA1320ATS
•
Low power consumption.
•
2.7 to 3.6 V power supply.
•
Selectable control via L3 microcontroller interface or via
static pin control.
•
256, 384 and 512f
s
system clock (f
sys
), selectable via
the L3 interface or 256 and 384f
s
clock mode via static
pin control
•
supports sampling frequencies from 16kHz to 48kHz.
•
Integrated digital filter plus non inverting DAC
Digital-to-Analog Converter (DAC).
•
Easy application and no analog post filtering required for
DAC.
•
Slave mode only applications.
•
Small package size (SSOP16).
1.2
Multiple format input interface
2
APPLICATIONS
•
Portable digital audio equipment, see Fig.8.
•
Set-top boxes
3
GENERAL DESCRIPTION
The UDA1320ATS/N2 is a single-chip non inverting stereo
DAC employing bitstream conversion techniques. The low
power consumption and low voltage requirements make
the device eminently suitable for use in digital audio
equipment which incorporates playback functions.
The UDA1320ATS/N2 supports the I
2
S-bus data format
with word lengths of up to 20 bits, the MSB-justified data
format with word lengths of up to 20 bits and the
LSB-justified serial data format with word lengths of 16,
18 and 20 bits.
The UDA1320ATS/N2 can be used in two modes, either
L3-mode or static pin mode.
In the L3-mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.
In the two static-modes, the UDA1320ATS/N2 can be
operated in the 256f
s
and 384f
s
system clock mode. The
mute, de-emphasis for 44.1 kHz and 4 digital input formats
(I
2
S and 16, 18, 20 bits LSB formats) can be selected via
static pins. The L3 interface cannot be used in this
application mode, also, volume control is not available in
this mode.
•
I
2
S-bus, MSB-justified and LSB-justified 16,18 and 20
bits format compatible (in L3-mode).
•
I
2
S-bus and LSB-justified 16,18 and 20 bits format
compatible in static mode.
•
1f
s
input format data rate.
1.3
DAC digital sound processing
•
Digital logarithmic volume control via L3.
•
Digital de-emphasis for 32, 44.1 and 48 kHz f
s
via
L3 or 44.1 kHz f
s
via static pin control.
•
Soft mute via static pin control or via L3 interface.
1.4
Advanced audio configuration
•
Stereo line output (under L3 volume control)
•
High linearity, wide dynamic range, low distortion.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT369-1
UDA1320ATS
SSOP16
2000 Jan 10
3
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
7
PINNING
SYMBOL
BCK
WS
DATAI
V
DDD
V
SSD
SYSCLK
APPSEL
APPL3
APPL2
APPL1
APPL0
V
REF(DAC)
V
DDA
V
O(L)
V
SSA
V
O(R)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
bit clock
word select
data input
digital power supply
digital ground
system clock: 256f
s
, 384f
s
, 512f
s
application mode select
application pin 3
application pin 2
application pin 1
application pin 0
DAC reference voltage
analog supply voltage
left output voltage
analog ground
right output voltage
DESCRIPTION
8
8.1
UDA1320ATS
FUNCTIONAL DESCRIPTION
System clock
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
The options are 256f
s
, 384f
s
and 512f
s
for the L3 mode
and 256f
s
plus 384f
s
for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
8.2
Application modes
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = V
SSD
) or to either of
two static modes (APPSEL = 0.5V
DDD
or
APPSEL = V
DDD
). See Table 1 for APPL0 to APPL3 pin
functions (active = HIGH).
Table 1
Selection modes via APPSEL (note 1)
APPSEL
PIN
V
SSD
0.5V
DDD
(384f
s
)
MUTE
DEEM
SF0
SF1
V
DDD
(256f
s
)
MUTE
DEEM
SF0
SF1
handbook, halfpage
BCK 1
WS 2
DATAI 3
VDDD 4
VSSD 5
SYSCLK 6
APPSEL 7
APPL3 8
MGM817
16 VO(R)
15 VSSA
14 VO(L)
APPL0
APPL1
APPL2
APPL3
TEST
L3CLOCK
L3MODE
L3DATA
UDA1320A
13 VDDA
12 VREF(DAC)
11 APPL0
10 APPL1
9
APPL2
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
In L3 mode pin APPL0 must be set to LOW.
Fig.2 Pin configuration.
2000 Jan 10
5
stm32/stm8
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