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EP20K1000EFC672-1N

Description
Loadable PLD, 1.84ns, CMOS, PBGA672, FINE LINE, BGA-672
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,132 Pages
ManufacturerAltera (Intel)
Environmental Compliance  
Download Datasheet Parametric View All

EP20K1000EFC672-1N Overview

Loadable PLD, 1.84ns, CMOS, PBGA672, FINE LINE, BGA-672

EP20K1000EFC672-1N Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAltera (Intel)
Parts packaging codeBGA
package instructionBGA,
Contacts672
Reach Compliance Codecompliant
maximum clock frequency160 MHz
JESD-30 codeS-PBGA-B672
JESD-609 codee1
length27 mm
Dedicated input times4
Number of I/O lines508
Number of terminals672
Maximum operating temperature85 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 508 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)245
Programmable logic typeLOADABLE PLD
propagation delay1.84 ns
Certification statusNot Qualified
Maximum seat height3.5 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width27 mm
APEX 20K
Programmable Logic
Device Family
March 2004, ver. 5.1
Data Sheet
Features
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
MultiCore
TM
architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
30,000 to 1.5 million typical gates (see
Tables 1
and
2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Note (1)
EP20K100
263,000
Table 1. APEX 20K Device Features
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E
113,000
EP20K60E
162,000
EP20K100E
263,000
EP20K160E
404,000
EP20K200
526,000
EP20K200E
526,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
100,000
4,160
26
53,248
416
252
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
200,000
8,320
52
106,496
832
382
200,000
8,320
52
106,496
832
376
Altera Corporation
DS-APEX20K-5.1
1

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