ORT82G5-2F680I datasheet, PDF - EEWORLD Datasheet

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ORT82G5-2F680I: DescriptionFPGA - Field Programmable Gate Array ORCA FPSC 2.7GBITS/s BP XCVR 643K; CategoryProgrammable logic devices Programmable logic; File Size557KB，119 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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ORT82G5-2F680I Overview

FPGA - Field Programmable Gate Array ORCA FPSC 2.7GBITS/s BP XCVR 643K

ORT82G5-2F680I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	PGA
package instruction	LEAD FREE, FPGA-680
Contacts	680
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	S-XBGA-B680
JESD-609 code	e0
Humidity sensitivity level	3
Number of terminals	680
Package body material	UNSPECIFIED
encapsulated code	BGA
Encapsulate equivalent code	BGA680,34X34,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
surface mount	YES
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

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ORCA

ORT42G5 and ORT82G5

0.6 to 3.7 Gbps

XAUI and FC FPSCs

July 2008

Data Sheet DS1027

Introduction

Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane

data transmission. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the

ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively.

Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous inter-

face with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K

usable FPGA system gates. The CDR circuitry available from Lattice’s high-speed I/O portfolio (sysHSI™), has

already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet

(GbE, 10 GbE) applications.

Designers can also use these devices to drive high-speed data transfer across buses within any generic system.

For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a

XAUI interface with a conﬁgurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be

used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and

protection links between a line card and switch fabric.

The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board

or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system perfor-

mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network

designers will beneﬁt from the backplane transceiver as a network termination device. The device supports embed-

ded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel.

The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of

SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5,

which implements four channels of SERDES with SONET scrambling and cell processing.

Table 1. ORCA ORT42G5 and ORT82G5 Family – Available FPGA Logic

Device

ORT42G5

ORT82G5

PFU Rows

PFU

Columns

Total PFUs

1296

FPGA Max.

User I/O

204

372

LUTs

10,368

EBR

Blocks

EBR Bits

(K)

111

FPGA System

Gates (K)

333-643

1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges

are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR

usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage

and four PLLs.

2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

DS1027_07.0

Lattice Semiconductor

ORCA ORT42G5 and ORT82G5 Data Sheet

Embedded Function Features

• High-speed SERDES with programmable serial data rates over the range 0.6 to 3.7 Gbps. Operation has been

demonstrated on design tolerance devices at 3.7 Gbps across 26 in. of FR-4 backplane and at 3.125 Gbps

across 40 in. of FR-4 backplane across temperature and voltage speciﬁcations.

• Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock

per block channels (separate PLL per channel).

• Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control

registers.

• Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application.

• Transmit preemphasis (programmable) for improved receive data eye opening.

• 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic.

• Provides a 10 Gbps backplane interface to switch fabric. Also supports multiple port cards at 2.5 Gbps.

• 3.125 Gbps SERDES compliant with XAUI serial data speciﬁcation for 10 G Ethernet applications with protec-

tion.

• IEEE 802.3ae compliant XAUI transceiver. Includes embedded IEEE 802.3ae-based XAUI link state machine.

• Compliant to FC-0 speciﬁcation for 1 Gbps, 2Gbps, 10 Gbps (FC-XAUI) modes. Includes Fibre Channel link state

machine.

• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external

clocks.

• SERDES has low-power CML buffers. Support for 1.5V/1.8V I/Os. Allows use with optical transceiver, coaxial

copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4.

• Power down option of SERDES HSI receiver or transmitter on a per-channel basis.

• Automatic lock to reference clock in the absence of valid receive data.

• High-speed and low-speed loopback test modes.

• Requires no external component for clock recovery and frequency synthesis.

• SERDES characterization pins available to control/monitor the internal interface to one SERDES block

(ORT82G5 only).

• SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating

state.

• Built-in boundary scan (IEEE

1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES

interface.

• FIFOs can align incoming data either across all eight channels (ORT82G5 only), across one or two groups of

four channels, or across two or four groups of two channels. Alignment is done either using comma characters or

by using the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous

operation between channels. (Each channel includes its own clock and frame pulse or comma detect.)

• Addition of two 4K x 36 dual-port RAMs with access to the programmable logic.

• The ORT82G5 is pinout compatible to the ORCA ORSO82G5 SONET backplane driver FPSC. The ORT42G5 is

pin compatible to the ORSO42G5.

Lattice Semiconductor

ORCA ORT42G5 and ORT82G5 Data Sheet

Programmable Features

• High-performance programmable logic:

– 0.16 µm 7-level metal technology.

– Internal performance of >250 MHz.

– Over 400K usable system gates.

– Meets multiple I/O interface standards.

– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.

• Traditional I/O selections:

– LVTTL (3.3V) and LVCMOS (2.5V and 1.8V) I/Os.

– Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance.

– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA

sink/3 mA source.

– Two slew rates supported (fast and slew-limited).

– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.

– Fast open-drain drive capability.

– Capability to register 3-state enable signal.

– Off-chip clock drive capability.

– Two-input function generator in output path.

• New programmable high-speed I/O:

– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.

– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100

) is also supported for these I/Os.

• New capability to (de)multiplex I/O signals:

– New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).

– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).

• Enhanced twin-block Programmable Function Unit (PFU):

– Eight 16-bit Look-Up Tables (LUTs) per PFU.

– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-

dently, plus one extra for arithmetic operations.

– New register control in each PFU has two independent programmable clocks, clock enables, local

SET/RESET, and data selects.

– New LUT structure allows ﬂexible combinations of LUT4, LUT5, new LUT6, 4

→

1 MUX, new 8

→

1 MUX,

and ripple mode arithmetic functions in the same PFU.

– 32 x 4 RAM per PFU, conﬁgurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in

only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.

– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast

internal routing which reduces routing congestion and improves speed.

– Flexible fast access to PFU inputs from routing.

– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-

tions, with the option to register the PFU carry-out.

• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over

previous architectures.

• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in

faster routing times with predictable and efﬁcient performance.

• SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PAL

-like AND-OR-Invert (AOI) in each pro-

grammable logic cell.

• New 200 MHz embedded block-port RAM blocks, two read ports, two write ports, and two sets of byte lane

enables. Each embedded RAM block can be conﬁgured as:

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