PACDN006
6 Channel ESD Protection Array
Features
•
•
•
•
•
•
•
Six channels of ESD protection
+
8 kV contact,
+
15 kV air ESD protection per
per channel (IEC 61000-4-2 standard)
+
15 kV of ESD protection per channel (HBM)
Low loading capacitance (3pF typical)
Low leakage current is ideal for battery-powered
devices
Available in miniature 8-pin MSOP or SOIC pack-
ages
Lead-free versions available
Product Description
The PACDN006 is a diode array designed to provide 6
channels of ESD protection for electronic components
or sub-systems. Each channel consists of a pair of
diodes which steers an ESD current pulse to either the
positive (V
P
) or negative (V
N
) supply. The PACDN006
protects against ESD pulses up to 15kV Human Body
Model (100 pF capacitor discharging through a 1.5KΩ
resistor), and 8kV contact discharge, per International
Standard IEC 61000-4-2.
This device is particularly well-suited for portable elec-
tronics (e.g., cellular phones, PDAs, notebook comput-
ers) because of its small package footprint, high ESD
protection level, and low loading capacitance. It is also
suitable for protecting video output lines and I/O ports
in computers and peripherals and is ideal for a wide
range of consumer electronics products.
The PACDN006 is available with optional lead-free fin-
ishing, supporting the current global industry move-
ment to lead free manufacturing.
Applications
•
•
•
•
•
•
•
Consumer electronic products
Cellular phones
PDAs
Notebook computers
Desktop PCs
Digital cameras and camcorders
VGA (video) port protection for desktop
and portable PCs
Typical Application Circuit
V
CC
3
7
Electrical Schematic
8
0.22uF*
7
VP
6
5
PACDN006
1 24 5 6 8
I/O Port
Buffers
Expansion
Connector
VN
Handheld/PDA ESD Protection
* Decoupling capacitor must be placed
as close as possible to Pin7.
1
2
3
4
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
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Fax: 408.263.7846
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www.calmicro.com
1
PACDN006
PACKAGE / PINOUT DIAGRAMS
TOP VIEW
CH 1
CH 2
V
N
CH 3
1
2
3
4
8
7
6
5
CH 6
V
P
CH 5
CH 4
CH 1
CH 2
V
N
CH 3
TOP VIEW
1
2
3
4
8
7
6
5
CH 6
V
P
CH 5
CH 4
8-pin MSOP
Note: MSOP and SOIC packages are different in size, pitch,
and proportion. These drawings are not to scale.
8-pin SOIC
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
NAME
CH 1
CH 2
V
N
CH 3
CH 4
CH 5
V
P
CH 6
TYPE
I/O
I/O
GND
I/O
I/O
I/O
Supply
I/O
DESCRIPTION
ESD Channel.
ESD Channel.
Negative voltage supply rail or ground reference rail.
ESD Channel.
ESD Channel.
ESD Channel.
Positive voltage supply rail.
ESD Channel.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Pins
8
8
Package
SOIC
MSOP
Ordering Part
Number
1
PACDN006S
PACDN006M
Part Marking
PDN006S
D006
Lead-free Finish
Ordering Part
Number
1
PACDN006SM
PACDN006MR
Part Marking
PACDN006SM
006R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
01/09/04
PACDN006
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (V
P
- V
N
)
Diode Forward DC Current (Note 1)
Operating Temperature Range
Storage Temperature Range
DC Voltage at any channel input
Package Power Rating
SOIC Package
MSOP Package
Note 1: Only one diode conducting at a time.
RATING
6.0
20
-40 to +85
-65 to +150
(V
N
- 0.5) to (V
P
+ 0.5)
350
200
UNITS
V
mA
°C
°C
V
mW
mW
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature Range
Operating Supply Voltage (V
P
- V
N
)
RATING
-40 to +85
0 to 5.5
UNITS
°C
V
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
I
P
V
F
V
ESD
PARAMETER
Supply Current
Diode Forward Voltage
ESD Protection
Peak Discharge Voltage at any channel
input, in system
a) Human Body Model, MIL-STD-883,
Method 3015
b) Contact Discharge per IEC 61000-4-2
c) Air Discharge per IEC 61000-4-2
Channel Clamp Voltage
Positive Transients
Negative Transients
Channel Leakage Current
Channel Input Capacitance
@ 1 MHz, V
P
=5V, V
N
=0V,
V
IN
=2.5V; Note 2 applies
CONDITIONS
(V
P
-V
N
)=5.5V
I
F
= 20mA
Note 3
Notes 2,4
Note 5
Note 5
@15kV ESD HBM
V
P
+ 13.0
V
N
- 13.0
+0.1
3
+1.0
5
V
V
µA
pF
+15
+8
+15
kV
kV
kV
0.65
MIN
TYP
MAX
10
0.95
UNITS
µA
V
V
CL
I
LEAK
C
IN
Note 1: All parameters specified at T
A
=25°C unless otherwise noted. V
P
= 5V, V
N
= 0V unless noted.
Note 2: These parameters guaranteed by design and characterization.
Note 3: From I/O pins to V
P
or V
N
only. V
P
bypassed to V
N
with a 0.22µF ceramic capacitor (see Application Information for more
details).
Note 4: Human Body Model per MIL-STD-883, Method 3015, C
Discharge
= 100pF, R
Discharge
= 1.5KΩ, V
P
= 5.0V, V
N
grounded.
Note 5: Standard IEC 61000-4-2 with C
Discharge
= 150pF, R
Discharge
= 330Ω, V
P
= 5.0V, V
N
grounded.
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
3
PACDN006
Performance Information
Input Capacitance vs. Input Voltage
5
4
CIN (pF)
3
2
1
0
0
1
2
3
4
5
VIN
(V
P
= 5V, V
N
= 0V, 0.1
µF
chip capacitor between V
P
and V
N
)
Typical Variation of C
IN
vs. V
IN
© 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
01/09/04
PACDN006
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to
Figure 1,
which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L
1
and L
2
. The volt-
age V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
)
/
dt
+ L
2
x d(I
ESD
)
/
dt
a R
OUT
of 1 ohm would result in a 10V increment in
V
CL
for a peak I
ESD
of 10A.
If the inductances and resistance described above are
close to zero, the rail-clamp ESD protection diodes will
do a good job of protection. However, since this is not
possible in practical situations, a bypass capacitor
must be used to absorb the very high frequency ESD
energy. So for any brand of rail-clamp ESD protection
diodes, a bypass capacitor should be connected
between the V
P
pin of the diodes and the ground plane
(V
N
pin of the diodes) as shown in the Application Cir-
cuit diagram below. A value of 0.22µF is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(
+
8kV). Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided
as they have poor high frequency characteristics. For
extra protection, connect a zener diode in parallel with
the bypass capacitor to mitigate the effects of the para-
sitic series inductance inherent in the capacitor. The
breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
where I
ESD
is the ESD current pulse, and V
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ESD
)/dt can be approximated by
∆I
ESD
/∆t, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
and L
2
combined) will lead to a 300V incre-
ment in V
CL
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V
CL
equation
above, the V
SUPPLY
term, in reality, is given by (V
DC
+
I
ESD
x R
OUT
), where V
DC
and R
OUT
are the nominal
supply DC output voltage and effective output imped-
ance of the power supply respectively. As an example,
V
P
Additional Information
See also California Micro Devices Application Notes
AP209, “Design Considerations for ESD Protection”
and AP219, "ESD Protection for USB 2.0 Systems"”
L
2
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I
ESD
0.22µF
D
1
ONE
CHANNEL
OF
PACDN006
L
1
CHANNEL
INPUT
20A
LINE BEING
PROTECTED
D
2
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
V
CL
GROUND RAIL
0A
V
N
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
© 2004 California Micro Devices Corp. All rights reserved.
01/09/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
5
Embedded System
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