CAT25010, CAT25020, CAT25040
1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM
FEATURES
10 MHz SPI compatible
1.8V to 5.5V supply voltage range
SPI modes (0,0) & (1,1)
16-byte page write buffer
Self-timed write cycle
Hardware and software protection
Block write protection
– Protect 1/4, 1/2 or entire EEPROM array
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial and Extended temperature range
RoHS-compliant 8-lead PDIP, SOIC, TSSOP and
8-pad TDFN packages
DESCRIPTION
The CAT25010/20/40 are 1-Kb/2-Kb/4-Kb Serial
CMOS EEPROM devices internally organized as
128x8/256x8/512x8 bits. They feature a 16-byte page
write buffer and support the Serial Peripheral Interface
(SPI) protocol. The device is enabled through a Chip
¯¯
Select (CS) input. In addition, the required bus signals
are a clock input (SCK), data input (SI) and data
¯¯¯¯¯
output (SO) lines. The HOLD input may be used to
pause any serial communication with the
CAT25010/20/40 device. These devices feature
software and hardware write protection, including
partial as well as full array protection.
PIN CONFIGURATION
PDIP (L)
SOIC (V)
TSSOP (Y)
TDFN (VP2)
¯¯
CS
SO
¯¯¯
WP
V
SS
1
2
3
4
8 V
CC
¯¯¯¯¯
7 HOLD
6 SCK
5 SI
SI
CS
WP
HOLD
SCK
CAT25010
CAT25020
CAT25040
SO
FUNCTIONAL SYMBOL
V
CC
PIN FUNCTION
Pin Name
¯¯
CS
SO
¯¯¯
WP
V
SS
SI
SCK
¯¯¯¯¯
HOLD
V
CC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
V
SS
For Ordering Information details, see page 16.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1006 Rev. T
CAT25010, CAT25020, CAT25040
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
Ratings
-65 to +150
-0.5 to V
CC
+ 0.5
Units
ºC
V
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, T
A
=-40°C to +125°C unless otherwise specified.
Symbol Parameter
I
CC
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Supply Current
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
> 2.5V, I
OL
= 3.0mA
V
CC
> 2.5V, I
OH
= -1.6mA
V
CC
> 1.8V, I
OL
= 150µA
V
CC
> 1.8V, I
OH
= -100µA
V
CC
- 0.2V
V
CC
- 0.8V
0.2
Test Conditions
Read, Write, V
CC
= 5.0V,
SO open
¯¯
V
IN
= GND or V
CC
, CS = V
CC
,
¯¯¯ = V
CC
, V
CC
= 5.0V
WP
¯¯
V
IN
= GND or V
CC
, CS = V
CC
,
¯¯¯ = GND, V
CC
= 5.0V
WP
V
IN
= GND or V
CC
¯¯
CS = V
CC
,
V
OUT
= GND or V
CC
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
-2
-1
-1
-0.5
0.7V
CC
10MHz / -40°C to 85°C
5MHz / -40°C to 125°C
Min
Max
2
2
2
4
5
2
1
2
0.3V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
PIN CAPACITANCE
(3)
T
A
= 25˚C, f = 1.0MHz, V
CC
= +5.0V
Symbol
C
OUT
C
IN
Test
Output Capacitance (SO)
¯¯
Input Capacitance (CS, SCK, SI, ¯¯¯, HOLD)
WP ¯¯¯¯¯
Conditions
V
OUT
= 0V
V
IN
= 0V
Min
Typ
Max
8
8
Units
pF
pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5V, 25°C
Doc. No. MD-1006 Rev. T
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
A.C. CHARACTERISTICS
T
A
= -40°C to +125°C, unless otherwise specified.
(1)
V
CC
= 1.8V-5.5V
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI(2)
t
FI(2)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
t
WC(4)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
¯¯¯¯¯
HOLD to Output Low Z
Input Rise Time
Input Fall Time
¯¯¯¯¯
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
¯¯¯¯¯
HOLD to Output High Z
¯¯
CS High Time
¯¯
CS Setup Time
¯¯
CS Hold Time
¯¯¯ Setup Time
WP
¯¯¯ Hold Time
WP
Write Cycle Time
50
50
50
10
10
5
0
50
100
15
15
15
10
10
5
0
10
75
0
20
25
Min.
DC
30
30
75
75
50
2
2
0
10
40
Max.
5
V
CC
= 2.5V-5.5V
T
A
= -40°C to +85°C
Min.
DC
20
20
40
40
25
2
2
Max.
10
Units
MHz
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Notes:
(1) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤
10ns
Input and output reference voltages: 0.5V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 50pF
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
¯¯
(4) t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1006 Rev. T
CAT25010, CAT25020, CAT25040
PIN DESCRIPTION
SI:
The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO:
The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25010/20/40.
¯¯
CS:
The chip select input pin is used to enable/disable
¯¯
the CAT25010/20/40. When CS is high, the SO output
is tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress).
Every communication session between host
and CAT25010/20/40 must be preceded by a high to
low transition and concluded with a low to high
¯¯
transition of the CS input.
¯¯¯:
The write protect input pin will allow all write
WP
operations to the device when held high. When ¯¯¯
WP
pin is tied low all write operations are inhibited.
¯¯¯¯¯
HOLD:
The ¯¯¯¯¯ input pin is used to pause trans–
HOLD
mission between host and CAT25010/20/40, without
having to retransmit the entire sequence at a later
¯¯¯¯¯
time. To pause, HOLD must be taken low and to
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
pausing, the ¯¯¯¯¯ input should be tied to V
CC
,
HOLD
either directly or through a resistor.
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0)
and (1,1). The device contains an 8-bit instruction
register. The instruction set and associated op-codes
are listed in Table 1.
Reading data stored in the CAT25010/20/40 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
¯¯
After a high to low transition on the CS input pin, the
CAT25010/20/40 will accept any one of the six
instruction op-codes listed in Table 1 and will ignore all
other possible 8-bit combinations. The communication
protocol follows the timing from Figure 1.
Table 1: Instruction Set
(1)
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 1. Synchronous Data Timing
V
IH
t
CS
CS
V
IL
V
IH
V
IL
V
IH
t
SU
t
CSS
t
CSH
SCK
t
WH
t
H
t
WL
SI
VALID IN
t
RI
tFI
VIL
t
V
t
HO
t
DIS
HI-Z
SO
V
OH
V
OL
HI-Z
Note:
Dashed Line = mode (1, 1) - - - - - -
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc. No. MD-1006 Rev. T
CAT25010, CAT25020, CAT25040
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The ¯¯¯¯ (Ready) bit indicates whether the device is
RDY
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
Table 2. Status Register
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
¯¯¯¯
RDY
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
Table 3. Block Protection Bits
Status Register Bits
BP1
0
0
BP0
0
1
Array Address Protected
None
CAT25010: 060-07F
CAT25020: 0C0-0FF
CAT25040: 180-1FF
CAT25010: 040-07F
CAT25020: 080-0FF
CAT25040: 100-1FF
CAT25010: 000-07F
CAT25020: 000-0FF
CAT25040: 000-1FF
Protection
No Protection
Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1006 Rev. T
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