530EB506M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530EB506M000DG

530EB506M000DG: DescriptionLVPECL Output Clock Oscillator, 506MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530EB506M000DG Overview

LVPECL Output Clock Oscillator, 506MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530EB506M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	506 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Radial wiring power supply circuit a

Normally closed contact anti-theft alarm

Automatically restore the power supply circuit after the low-voltage circuit breaker trips

2x voltage circuit diagram

Simple multipurpose electronic regulator circuit

Anti-theft and anti-eavesdropping telephone line protector circuit diagram

Which of the two ways of making differential lines of equal length internally is better?: As shown in the two pictures below, the first method is to use a bend to make up for the equal length error of the differential lines. The second method is to slightly increase the spacing between the...; lingking PCB Design

Seniors: Is there any senior who knows about the stcstc89c52rc microcontroller? I am learning it myself. If you have any information on learning microcontroller programming, please share it with me. Thank you...; 北夷蛮荒 Talking

Program for MSP430F5529 and MAX7456 character overlay module: [i=s]This post was last edited by fish001 on 2019-8-8 22:51[/i]I didn't use Keil, I used IAR. The MCU source code is as follows:#include msp430f5529.h#include "SPI.h"#include "MAX7456.h" #define uint ...; fish001 Microcontroller MCU

Qt Learning Road 16 Standard Dialog Box QMessageBox: In the previous chapters (Signals and Slots and Custom Signals and Slots), we introduced the new syntax of signals and slots in Qt 5 in detail. Since this change is large, many problems that did not s...; 兰博 Embedded System

Looking for AT91SAM7S64 evaluation board routines: Dear experts, I am eager to find the AT91SAM7S64 evaluation board routine. I hope some friends can send it to me. Thank you very much:):), or send it to my email [url=mailto:whwshiyuan@126.com]whwshiy...; whwshiyuan1984 MCU

Arteli SC0034AT32F4xx_CAN filter usage: Example PurposeDemonstrates the use of AT32F4xx_CAN filter. The filter is mainly used to selectively receive messages. Supported models:AT32F403xxAT32F403AxxAT32F407xxAT32F413xxAT32F415xx Main periphe...; 火辣西米秀 Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components