OKI Semiconductor
ML87V3104
LCD Display Controller with Embedded Display Memory
FEDL87V3104-03
Issue Date: Nov. 28, 2003
GENERAL DESCRIPTION
The ML87V3104 is an LCD graphic display controller intended for use in medium to small-sized equipment
having such as QVGA grade medium-sized LCD panels, such as PDA or portable information terminals.
Since this LSI device has an internal display memory, use of this device reduces the component count. It is
possible to set an easy to use configuration of the display memory size, such as 1024
×
1024 dots
×
4 bits or 2048
×
256 dots
×
8 bits, depending on the application at hand, and it is possible to access the image data without having
to be concerned about address conversion.
The area specified in the display memory can be output on the display.
The display data and the control information can be set by the host CPU.
FEATURES
•
Display memory:
•
Display size:
•
Number of display colors:
•
Color palette:
•
Output data:
•
Display functions:
Horizontal 4096 dots, maximum, vertical 4096 dots, maximum (with restrictions)
Horizontal 1024 dots, maximum, vertical 1024 dots, maximum (with restrictions)
suitable for QVGA (320
×
240) or HVGA (640
×
240, 480
×
320)
16/256 Colors out of 4096 colors (pseudo-colors)
4096/65536 Colors (direct colors)
256 Colors
×
12 bits (R4, G4, B4)
STN 4/8 bits parallel,
TFT 12 bits (R4, G4, B4) / 16 bits (R5, G6, B5)
Scroll (in units of 16 horizontal pixels and 1 vertical line),
Sub-screen display (any position, pseudo-color mode only)
Hardware cursor (16
×
16
×
2 bits)
Duty 1/64 to 1/1024, up to 16-gray levels,
Programmable AC driving signal (Toggle period can be specified.)
(68k- Series, 80-Series, RISCs of different companies, etc.)
4M bit DRAM
15 MHz, maximum
3.3 V
±
0.3 V
100-Pin plastic TQFP (TQFP100-P-1414-0.50-K)
•
LCD Drive signals:
•
Host CPU: 8/16 bits
•
Embedded memory:
•
Operating frequency:
•
Power supply voltages:
•
Package:
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
BLOCK DIAGRAM
Display
Memory
(4M bit DRAM)
ADRS
C
CPU
Bus
(8/16bits)
P
U
I/F
Config.
Reg.
Conv.
Memory
Controller
Color
Palette
Output
Format
to LCD
Cursor Gen.
Timing Gen.
LCD Interface
LCD control
signals
APPLICATION CIRCUIT
The following is an example of application to a handy terminal for POS systems.
Key
16-bit
MCU
RAM
ROM
PC
Card
Barcode
Serial I/F
Scanner
System
BUS
ML87V3104
QVGA
Color STN
LCD module
Touch Panel
Peripheral
Interface
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
PIN CONFIGURATION (TOP VIEW)
100-pin Plastic TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D00
D01
D02
D03
VDDI
D04
D05
D06
D07
(NC)
(NC)
(NC)
VSS
AD00
AD01
VDDI
AD02
AD03
AD04
AD05
VSS
AD06
AD07
AD08
AD09
(NC)
CSN
REN
WEN
BSN
VSS
DSN
BSYN
REGS
BCLK
VDDI
XOSCI
(NC)
XOSCO
VSS
RESETN
(NC)
HMOD3
HMOD2
VDDI
HMOD1
HMOD0
TEST1
TEST0
(NC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TQFP100-P-1414-0.50-K
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(NC)
AD10
AD11
(NC)
AD12
AD13
(NC)
VDDI
AD14
AD15
A16
A17
VSS
A18
VDDI
PORT1
PORT0
(TOUT)
(NC)
VSS
DDD0
DDD1
DDD2
DDD3
(NC)
NC: No-connection pins These pins should be left open during normal use.
Please supply the same voltage to all the “VDDI” pins, also “VDDO” pins.
(NC)
DISP
DF
FRP
LCP
VSS
DDA3
DDA2
DDA1
DDA0
VDDO
CPS
CP
(NC)
VSS
(NC)
DDB3
DDB2
DDB1
DDB0
VDDO
DDC3
DDC2
DDC1
DDC0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
PIN DESCRIPTIONS
Table P1. List of pins and their descriptions
Pin
Symbol
I/O
Type
27
28
29
30
32-35
37
38
42-45
47-50
52-55
59, 60
62, 64, 65
66, 67, 70, 71
73, 74, 76-79
81-84, 86, 87
92-95, 97-100
2
3
4
5
7
8
10
9
12
14
16
18, 19, 21, 22
23, 24
58
11, 20, 61, 68,
85, 96
36, 46
6, 15, 31, 40,
56, 63, 80, 88
DISP
DF
FRP
LCP
DDA3 - 0
CPS
CP
DDB3 - 0
DDC3 - 0
DDD3 - 0
PORT0, 1
A18 - 16
AD15 - 00
O
O
O
O
O
O
O
O
O
O
I/O
I
I/O
4mA drive
4mA drive
4mA drive
4mA drive
4mA drive
3-state
4mA drive
4mA drive
4mA drive
3-state
4mA drive
3-state
4mA drive
3-state
LVTTL /
4mA drive
LVTTL
LVTTL /
4mA drive
LVTTL /
4mA drive
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
LVTTL, Schmitt
8mA drive
3-state
LVTTL, Schmitt
LVTTL, Schmitt
X’tal oscillation
buffer
LVTTL
LVTTL
LVTTL
2mA drive
Power Supply
Power Supply
Power Supply
Description
LCD Display enable
LCD AC driving signal pin
LCD Frame pulse
LCD Line clock pulse
LCD Data A
LCD Data clock pulse 2 or Data Strobe
LCD Data clock pulse
LCD Data B
LCD Data C
LCD Data D
General purpose I/O port (input / output direction
can be set for each pin)
Host address bus
Host address/data multiplexed bus
D07 - 00
CSN
REN
WEN
BSN
DSN
BSYN
BCLK
REGS
XOSCI
XOSCO
RESETN
HMOD3 - 0
TEST1, 0
(TOUT)
VDDI
VDDO
VSS
I/O
I
I
I
I
I
O
I
I
I
O
I
I
I
O
—
—
—
Host data bus
Chip select (active “L”)
Read enable (active “L”)
Write enable (active “L”)
Bus start/address strobe (active “L”)
Data strobe (active “L”)
Busy/wait (active “L”, 3-stated)
Bus clock
Register select
Clock oscillator input (built-in feedback resistor)
Clock oscillator output
System reset (active “L”)
Host mode select
Test mode select (normally tied to “L”)
(Test output. Not used.)
Power supply for the internal core and I/O
Power supply for the LCD interface signal outputs
Common ground
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FEDL87V3104-03
OKI Semiconductor
ML87V3104
FUNCTIONAL DESCRIPTION
1. Display Memory
The address and data configuration of the display memory is specified by making control register settings.
When the defined memory size is smaller than the internal DRAM (4M bits), the page mode operation is started
automatically, making it possible to specify the display address in units of a page and to access the host CPU (a
maximum of 256 pages). Even when the address space of the host CPU bus is smaller than the display memory
space, the entire area can be accessed using the page mode.
There are limitations on the LCD drive mode depending on the display memory data width. (See Section 3.1.)
Note that the LCD control timings must be defined before accessing the display memory. (See Section 3.1.2)
•
Control registers:
IMASZX [#03h: bit 3-0]:
IMASZY [#03h: bit 7-4]:
IMDBPP [#02h: bit 1-0]:
HSTPGA [#3Bh]:
Display memory horizontal size (2
n
) (Table F1.1)
Display memory vertical size (2
n
)
(Table F1.1)
Number of bits per pixel
(Table F1.2)
Page number for host access
Table F1.1 Display memory size selection
IMASZY
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
Vertical size
(lines)
64
128
256
512
1024
2048
4096
(Reserved)
(Reserved)
IMASZX
0000
0001
0010
0011
0100
0101
0110
0111
1XXX
Horizontal size
(pixels)
64
128
256
512
1024
2048
4096
(Reserved)
(Reserved)
Table F1.2 Display memory data width
IMDBPP
00X
010
011
100
Number of bits
(bits / pixel)
—
4
8
16*
1
Pseudo color
Direct color
Number of simultaneously displayed colors
Color mode
—
16/4096
256/4096
4096
65536
Monochrome mode
—
16
256
—
—
Applicable
LCD type
—
STN/TFT
STN
TFT
*1: Correspondence between the display memory data and the color data in the 16BPP mode.
7
Upper byte
(no use)
0
7
Lower byte
0
STN 16 BPP
(12)
7
R R R R
3 2 1 0
0
G G G G B B B B
3 2 1 0 3 2 1 0
7
Upper byte
Lower byte
0
TFT 16 BPP
R R R R R G G G
5 4 3 2 1 5 4 3
G G G B B B B B
2 1 0 5 4 3 2 1
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