HM11S130
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
July. 12. 2000
VER 2.0
Hynix Semiconductor, Inc.
65COM / 132SEG DRIVER & CONTROLLER
FOR STN LCD
HM11S130
Preliminary Version 2.0
Version
0.1
HM11S130 Specification revision history
Content
1. LCD driving voltage range : V
LCD
= 4.0V ~ 15.0V
→
4.5V ~ 15.0V
2. TCP pin layout: FR, NC0, NC1
1. Chip size: 9540 x 2310µm (with S/L 100µm)
2. Remove the PAD: Total PAD 322ea
→
320ea (DUMMY 2ea)
1. ILB key position: 3953 x –298
→
3960 x –305
-3960 x 425
→
-3960 x 415
1.
Main VSS pad (PAD No. 41,42,43,44 and 45) have to be connected
Date
March. 2000
1.0
May. 2000
1.1
1.2
1.3
May. 2000
May.27.2000
1. Page 8 : COG key size miss print (30µm
→
60µm)
Page 33 : Reset circuit (normal
→
normal = 0)
Page 56 : Serial interface (insert: E_/RD, RW_/WR = “H or L”)
1. page 8 : Bumped pad size (40x60µm
→
40x102µm)
2. Page 9~11 : pad center coordinates
2.0
July.12.2000
Copyright © 2000, Hynix Semiconductor, Inc.
65COM / 132SEG DRIVER & CONTROLLER
FOR STN LCD
HM11S130
Preliminary Version 2.0
CONTENTS
1. INTRODUCTION
2. FEATURES
-----------------------------------------------------------------------------------------------------------
5
5
7
8
9
12
16
16
---------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
3. BLOCK DIAGRAM
4. PAD CONFIGURATION
------------------------------------------------------------------------------------------------
4-1. Pad center coordinates -------------------------------------------------------------------------------------------
5. PIN DESCRIPTION
----------------------------------------------------------------------------------------------------
6. FUNCTIONAL DESCRIPTION
-----------------------------------------------------------------------------------
6-1. Microprocessor interface ----------------------------------------------------------------------------------------
a. Chip select input
b. Interface
c. Parallel interface (PS = "H")
d. Serial interface (PS = "L")
e. Busy flag
f. Data accessing
6-2. Display data RAM (DDRAM) --------------------------------------------------------------------------------------
a. Display data RAM
b. Page address circuit
c. Column address circuit
d. Line address circuit
e. Segment control circuit
6-3. LCD display circuit ----------------------------------------------------------------------------------------------------
a. Oscillator
b. Display timing generator circuit
c. Common output control circuit
6-4. LCD driver circuit ---------------------------------------------------------------------------------------------------
6-5. Power supply circuits -------------------------------------------------------------------------------------------
a.
Voltage converter circuits
b.
Voltage regulator circuits
c.
Voltage follower circuits
d.
High power mode
6-6. Reference circuit examples --------------------------------------------------------------------------------------
6-7. Reset circuit --------------------------------------------------------------------------------------------------------
7. PROGRAM INSTRUCTION
----------------------------------------------------------------------------------------
7-1. Read display data -------------------------------------------------------------------------------------------------
7-2. Write display data ------------------------------------------------------------------------------------------------
7-3. Read status ----------------------------------------------------------------- ---------------------------------------
7-4. Display ON / OFF -----------------------------------------------------------------------------------------------------
7-5. Initial display line -------------------------------------------------------------------------------------------------
7-6. Reference voltage select --------------------------------------------------------------------------------------
7-7. Set page address ------------------------------------------------------------------------------------------------
7-8. Set column address -----------------------------------------------------------------------------------------------
7-9. ADC select ---------------------------------------------------------------------------------------------------------
7-10. Reverse display ON / OFF-----------------------------------------------------------------------------------------
7-11. Entire display ON / OFF--------------------------------------------------------------------------------------------
7-12. Select LCD bias --------------------------------------------------------------------------------------------------
7-13. Set modify-read ---------------------------------------------------------------------------------------------------
7-14. Reset modify-read -----------------------------------------------------------------------------------------------
7-15. Reset ----------------------------------------------------------------------------------------------------------------
7-16. SHL select ----------------------------------------------------------------------------------------------------------
19
22
23
24
31
32
34
35
35
36
36
37
37
38
39
39
39
40
40
40
40
41
41
Copyright © 2000, Hynix Semiconductor, Inc.
65COM / 132SEG DRIVER & CONTROLLER
FOR STN LCD
HM11S130
Preliminary Version 2.0
7-17. Power control ---------------------------------------------------------------------------------------------------------
7-18. Regulator resistor select ------------------------------------------------------------------------------------------
7-19. Set static indicator state -------------------------------------------------------------------------------------------
7-20. NOP -----------------------------------------------------------------------------------------------------------------------
7-21. Test instruction ---------------------------------------------------------------------------------------------------------
7-22. Power save (Compound instruction) ---------------------------------------------------------------------------
7-23. Referential instruction set flow-----------------------------------------------------------------------------------
8. SPECIFICATIONS
--------------------------------------------------------------------------------------------------------
8-1. Absolute maximum ratings ---------------------------------------------------------------------------------------
8-2. DC characteristics ----------------------------------------------------------------------------------------------------
8-3. AC characteristics --------------------------------------------------------------------------------------------------
a. Read / write characteristics (8080-series MPU)
b. Read / write characteristics (6800-series MPU)
c. Serial interface characteristics
d. Reset input timing
e. Display control output timing
9. REFERENCE APPLICATION
---------------------------------------------------------------------------------------------
9-1. MPU interface -------------------------------------------------------------------------------------------------------
9-2. Connections between HM11S130 and LCD panel -----------------------------------------------------------------
9-3. TCP pin layout (sample) -----------------------------------------------------------------------------------------
9-4. Application circuit for serial --------------------------------------------------------------------------------------
42
42
43
43
43
44
45
49
49
49
50
56
56
57
63
64
Copyright © 2000, Hynix Semiconductor, Inc.
65COM / 132SEG DRIVER & CONTROLLER
FOR STN LCD
HM11S130
Preliminary Version 2.0
1. INTRODUCTION
The HM11S130 i s a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It
contains 65 common and 132 segment driver circuits. This chip is connected directly to a microprocessor
(MPU), accepts serial or 8-bit parallel display data and stores in an on-chip Display Data RAM (DDRAM) of
65 x 132 bits. It provides a high-flexible display section due to one to one correspondences between on-
chip DDRAM bits and LCD panel pixels. And it performs DDRAM read / write operation with no externally
operating clock to minimize power consumption. In addition, because it contains power supply circuits
necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver output circuits
-. 65 common outputs / 132 segment outputs
On-chip display data RAM (DDRAM)
-. Capacity: 65 x 132=8,580 bits
-. RAM bit data “1”: a dot of display is illuminated.
-. RAM bit data “0”: a dot of display is not illuminated.
Multi-chip operation
-. Master and slave mode available
Applicable duty-ratios
Duty ratio
1/65
1/55
1/49
1/33
Applicable LCD bias
1/9 or 1/7
1/8 or 1/6
1/8 or 1/6
1/6 or 1/5
Maximum display area
65 x 132
55 x 132
49 x 132
33 x 132
Microprocessor (MPU) interface
-. High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series
-. Serial inter-face (only write operation) available
Various Function set
-. Display ON/OFF, set initial display line, set page address, set column address, read status, write /
read display data, select segment driver output, reverse display ON/OFF, entire display ON/OFF,
select LCD bias, set/reset modify-read, select common driver output, control display power circuit,
select internal regulator resistor ratio for V0 voltage regulation, electronic volume, set static
indicator state.
-. H/W and S/W reset available
-. Static drive circuit equipped internally for indicators with 4 flashing modes
Built-in analog circuits
-. On-chip Oscillator circuit for display clock(external clock can also be used)
-. High performance voltage converter
(with booster ratios of x2, x3, x4 and x5, where the step-up reference voltage can be used
externally)
-. High accuracy voltage regulator(temperature coefficient: -0.05%/℃ or external input)
-. Electronic contrast control function (64 steps)
-. Vref = 2.1V
±
3% (V0 voltage adjustment voltage)
-. High performance voltage follower
(V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity)
Copyright © 2000, Hynix Semiconductor, Inc.