HV5308B/HV5408B
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
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Processed with HVCMOS® technology
Low power level shifting
Source/sink current minimum 20mA
Shift register speed 8MHz
Latched data outputs
CMOS compatible inputs
Forward and reverse shifting options
Diode to V
PP
allows efficient power recovery
General Description
The HV5308B and HV5408B are low voltage serial to high
voltage parallel converters with push-pull outputs. These
devices have been designed for use as drivers for AC-
electroluminescent displays. They can also be used in any
application requiring multiple output high voltage current
sourcing and sinking capabilities, such as driving plasma
panels, vacuum fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to enable outputs. Q1 is connected to the first
stage of the shift register through the Output Enable logic. Data
is shifted through the shift register on the low to high transition
of the clock. The HV5408B shifts in the counterclockwise
direction when viewed from the top of the package, while the
HV5308B shifts in the clockwise direction. A data output buffer
is provided for cascading devices. This output reflects the
current status of the last bit of the shift register (32). Operation
of the shift register is not affected by the LE (latch enable) or
the OE (output enable) inputs. Transfer of data from the shift
register to the latch occurs when the LE input is high. The
data in the latch is retained when LE is low.
Typical Application Circuit
Low Voltage
Power Supply
Data Input
CLK
LE
Micro
Processor
OE
Shift Register
Latches
Output Contr.
Low Voltage
High Voltage
Level
Translators
&
Push-Pull
Output
Buffers
High Voltage
Power Supply
HV
OUT
1
Columns
Row
Driver
HV
OUT
32
Data Out
Display
Panel
Supertex HV5803B/ HV5804B
Data Input for cascading the next HV5308B/HV5408B
HV5308B/HV5408B
Ordering Information
Package Options
Device
44-J Lead Quad
Ceramic Chip Carrier
HV5308DJ-B
-
HV5408DJ-B
-
44-J Lead Quad
Ceramic Chip Carrier
(MIL-STD-883 Processed)
44-J Lead Quad
Plastic Chip Carrier
HV5308PJ-B
HV5308BPJ-B-G
HV5408PJ-B
HV5408PJ-B-G
44-Lead Quad
Plastic Gullwing
HV5308PG-B
HV5308PG-B-G
HV5408PG-B
HV5408PG-B-G
HV5308B
HV5308DJ-B
-
HV5408DJ-B
-
HV5408B
-G indicates package is RoHS compliant (‘Green’)
Pin Configurations
39 38 37 36 35 34 33 32 31 30 29
40
41
42
43
28
27
26
25
24
23
22
21
20
19
18
7
8
9 10 11 12 13 14 15 16 17
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
2
Ground current
3
Continuous total power dissipation
1
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16
inch) from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to GND.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.
2
44
1
2
3
4
Value
-0.5V to +16V
-0.5V to +90V
-0.5V to VDD + 0.5V
1.5A
Plastic
Ceramic
Plastic
Ceramic
1200W
1500W
-40
O
C to +85
O
C
-55
O
C to +125
O
C
-65
O
C to +150
O
C
260 C
O
5
6
44-J Lead Quad Ceramic Chip Carrier (DJ)
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
33
32
31
30
29
28
27
26
25
24
23
44-Lead Quad Plastic Gullwing (PG)
39 38 37 36 35 34 33 32 31 30 29
40
28
27
26
25
24
23
22
21
20
19
18
7
8
9 10 11 12 13 14 15 16 17
Recommended Operating Conditions
(Over -40 C to 85 C for plastic and -55 C to 125 C for ceramic)
O
O
O
O
41
42
43
44
Symbol
V
DD
V
PP
V
IH
V
IL
f
CLK
Parameter
Logic voltage supply
High voltage supply
Input HIGH voltage
Input Low voltage
Clock frequency
Min
10.8
8.0
V
DD
- 2
0
0
Max
13.2
80
V
DD
2
8
Units
V
V
V
V
MHz
1
2
3
4
5
6
44-J Lead Quad Plastic Chip Carrier (PJ)
2
HV5308B/HV5408B
Power-Up Sequence
1.
2.
3.
4.
Connect ground
Apply V
DD
Set all inputs (Data, CLK, LE, etc.) to a known state
Apply V
PP
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(V
DC Characteristics
Symbol
I
PP
I
DDQ
I
DD
V
OL
(Data)
I
IH
I
IL
V
OC
V
OH
V
OL
V
OH
V
OL
Parameter
V
PP
supply current
PP
= 60V, V
DD
= 12V, T
A
= 25°C)
Min
-
-
-
10.5
-
-
-
-
52
-
52
-
Max
0.5
100
15
-
1
1
-1
-1.5
-
8
-
8
Units
mA
µA
mA
V
V
µA
µA
V
V
V
V
V
Conditions
HV
OUTPUTS
HIGH to LOW
All inputs = V
DD
or GND
V
DD
= V
DD
max, f
CLK
= 8 MHz
I
O
= 100µA
I
O
= 100µA
V
IN
= V
DD
V
IN
= 0
I
OL
= -100mA
I
OH
= -20mA, -40 to 85°C
I
OL
= 20mA, -40 to 85°C
I
OH
= -15mA, -55 to 125°C
I
OL
= 15mA, -55 to 125°C
I
DD
supply current (quiescent)
I
DD
supply current (operating)
Shift register output voltage
Current leakage, any input
Current leakage, any input
HV output clamp diode voltage
HV output when sourcing
HV output when sinking
HV output when sourcing
HV output when sinking
V
OH
(Data) Shift register output voltage
AC Characteristics
Symbol
f
CLK
t
WL
or t
WH
t
SU
t
H
t
DLH
(Data)
t
DHL
(Data)
t
DLE
t
WLE
t
SLE
t
ON
t
OFF
Parameter
Clock frequency
Clock width, HIGH or LOW
Setup time before CLK rises
Hold time after CLK rises
Data output delay after L to H CLK
Data output delay after H to L CLK
LE delay after L to H CLK
Width of LE pulse
LE setup time before L to H CLK
Delay from LE to HV
OUT
, L to H
Delay from LE to HV
OUT
, H to L
Min
-
62
25
10
-
-
50
50
50
-
-
Max
8
-
-
-
110
110
-
-
-
500
500
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
---
---
---
---
CL = 15pF
CL = 15pF
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---
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3
HV5308B/HV5408B
Input and Output Equivalent Circuits
V
DD
V
DD
V
PP
Input
Data Out
HV
OUT
GND
Logic Inputs
GND
Logic Data Output
GND
High Voltage Outputs
Switching Waveforms
V
IH
Data Input
50%
t
SU
CLK
50%
t
WL
50%
t
WH
50%
V
OL
Data Out
t
DLH
50%
t
DHL
V
OH
V
OL
Data Valid
t
H
V
IH
50%
50%
V
IL
V
OH
50%
V
IL
50%
LE
t
DLE
t
WLE
50%
t
SLE
V
IH
V
OL
Q
w/ S/R LOW
t
OFF
Q
w/ S/R HIGH
90%
10%
V
OH
V
OL
10%
t
ON
90%
V
OH
V
OL
4
HV5308B/HV5408B
Functional Block Diagram
V
PP
OE
LE
Data Input
HV
OUT
1
CLK
32 Bit
Shift
Register
32
Latches
HV
OUT
2
•
•
•
32 Outputs Total
•
•
•
HV
OUT
31
Data Out
HV
OUT
32
Function Tables
Data Input
X
X
H
No
CLK
Data Output
H
L
No change
Data Input
X
X
H
L
LE
X
L
H
H
OE
L
H
H
H
HV Output
All HV
OUT
= LOW
Previous latched data
H
L
Pin Description
Pin Name
CLK
LE
Function
Data shift register clock
Latch enable input
Description
Input are shifted into the shift register on the positive edge of the clock.
When LE is HIGH, shift register data is transferred into a data latch.
When LE is LOW, data is latched, and new data can be clocked into the
shift register.
When OE is LOW, all HV outputs are forced into a LOW state, regardless
of data in each channel. When OE is HIGH, all HV outputs reflect data
latched.
Data needs to be present before each rising edge of the clock.
Data output for cascading to the data input of the next device.
High voltage push-pull outputs, which, depending on controlling low
voltage data, can drive loads either to a GND, or to V
PP
rail levels.
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5
OE
Data input
Data output
HV
OUT
(1-32)
GND
V
DD
V
PP
Output enable input
Serial data input
Serial data output
High voltage outputs
Logic and high voltage
ground
Low voltage logic power rail
High voltage power rail
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