To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the S12 CPU. For
S12 CPU information please refer to the CPU S12 Reference Manual.
Revision History
Date
June, 2005
July, 2005
Revision
Level
01.14
01.15
New Book
Removed 16MHz option for 128K, 96K and 64K versions
Minor corrections following review
Added outstanding flash module descriptions
Added EPP package options
Corrected and Enhanced recommended PCB layouts
Added note to PIM block diagram figure
Added PIM rerouting information to 80-pin package diagram
Modified LVI levels in electrical parameter section
Corrected TSCR2 typo in timer register listing
Cleaned up Device Overview Section
Description
Oct, 2005
Dec, 2005
Dec, 2005
Jan, 2006
Mar, 2006
01.16
01.17
01.18
01.19
01.20
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
4
MC9S12C-Family / MC9S12GC-Family
Rev 01.20
Freescale Semiconductor
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
MC9S12C and MC9S12GC Device Overview (MC9S12C128) . 19
Port Integration Module (PIM9C32). . . . . . . . . . . . . . . . . . . . . 77
Module Mapping Control (MMCV4) . . . . . . . . . . . . . . . . . . . . 113
Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . . 133
Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Background Debug Module (BDMV4). . . . . . . . . . . . . . . . . . 169
Debug Module (DBGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Analog-to-Digital Converter (ATD10B8CV2) . . . . . . . . . . . . . 227
Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . 253
Scalable Controller Area Network (S12MSCANV2) . . . . . . . . 289
Oscillator (OSCV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Pulse-Width Modulator (PWM8B6CV1) . . . . . . . . . . . . . . . . . 349
Serial Communications Interface (S12SCIV2) . . . . . . . . . . . . 385
Serial Peripheral Interface (SPIV3) . . . . . . . . . . . . . . . . . . . . . 415
Timer Module (TIM16B8CV1) . . . . . . . . . . . . . . . . . . . . . . . . . 437
Dual Output Voltage Regulator (VREG3V3V2) . . . . . . . . . . . 463
16 Kbyte Flash Module (S12FTS16KV1) . . . . . . . . . . . . . . . . . 471
32 Kbyte Flash Module (S12FTS32KV1) . . . . . . . . . . . . . . . . . 503
64 Kbyte Flash Module (S12FTS64KV4) . . . . . . . . . . . . . . . . . 537
96 Kbyte Flash Module (S12FTS96KV1) . . . . . . . . . . . . . . . . . 571
128 Kbyte Flash Module (S12FTS128K1V1) . . . . . . . . . . . . . . 605
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Appendix B Emulation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
,
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
Rev 01.20
5
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