Z
ILOG
P R E L I M I N A R Y
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
FEATURES
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s
s
s
s
s
s
s
16-Bit Single Cycle Instructions
Zero Overhead Hardware Looping
16-Bit Data
Ready Control for Slow Peripherals
Single Cycle Multiply/Accumulate (100 ns)
Six-Level Stack
512 Words of On-Chip RAM
Static Single-Cycle Operation
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s
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16-Bit I/O Port
4K Words of On-Chip Masked ROM
Three Vectored Interrupts
64K Words of External Program Address Space
Two Conditional Branch Inputs/Two User Outputs
24-Bit ALU, Accumulator and Shifter
IBM
®
PC Development Tools
GENERAL DESCRIPTION
The Z89C00 is a second generation, 16-bit, fractional,
two’s complement CMOS Digital Signal Processor (DSP).
Most instructions, including multiply and accumulate,
are accomplished in a single clock cycle. The processor
contains 1 Kbyte of on-chip data RAM (two blocks of
256 16-bit words), 4K words of program ROM and 64K
words of program memory addressing capability. Also,
the processor features a 24-bit ALU, a 16 x 16 multiplier, a
24-bit Accumulator and a shifter. Additionally, the processor
contains a six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of three pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be
simultaneously addressed and loaded to the multiplier for
a true single cycle multiply.
There is a 16-bit address and a 16-bit data bus for external
program memory and data, and a 16-bit I/O bus for
transferring data. Additionally, there are two general
purpose user inputs and two user outputs. Operation with
slow peripherals is accomplished with a ready input pin.
The clock may be stopped to conserve power.
Development tools for the IBM PC include a relocatable
assembler, a linker loader, and an ANSI-C compiler. Also,
the development tools include a simulator/debugger, a
cross assembler for the TMS320 family assembly code
and a hardware emulator.
To assist the user in understanding the Z89C00 DSP Q15
two's complement fractional multiplication, an application
note has been included in this product specification as an
appendix.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DC 4083-00
1
2
Z
ILOG
External Program ROM
PD15-PD0
16
16
PA
/ROMEN
PD
16
16
PC
256 Word
RAM
1
Instruction
Register
16
EXT15-EXT0
D-Bus
Switch
Y
PA15-PA0
GENERAL DESCRIPTION
(Continued)
Register
Pointer
0-2
256 Word
RAM
0
Register
Pointer
4-6
4K
Word
ROM
16-Bit Bus
/RDYE
2
ER//W, /EI
3
EA2-EA0
S-Bus
Ready
Switch
Stack
16-bit
I/O
Port
X
16 x16
Multiplier
24-bit
P
24
P-Bus
3
Interrupt
INT2-INT0
/RESET
P R E L I M I N A R Y
Figure 1. Functional Block Diagram
Shifter
Status
(5)
User
Port
A
24-Bit Bus
MUX
2
UI1-UI0
2
UO1-UO0
B
ALU
ACC
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
DC 4083-00
Z
ILOG
P R E L I M I N A R Y
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
EXT 15
EXT13
EXT 10
EXT 11
EXT14
EXT12
EXT9
EXT8
EXT7
EXT6
EXT5
EXT3
EXT2
EXT4
EXT1
9
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
UO1
UO0
INT2
INT1
INT0
UI1
UI0
HALT
/ROMEN
CLK
/RES
/RDYE
ER//W
/EI
EA2
EA1
EA0
Z89C00
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PA11
PA10
PA12
PA13
PA14
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
Figure 2. 68-Pin PLCC Pin Assignments
DC 4083-00
PA15
VDD
EXT0
52
51
50
49
48
47
46
45
44
VSS
3
Z
ILOG
P R E L I M I N A R Y
Table 1. 68-Pin PLCC Pin Identification
No.
1-9
10
11-26
27-38
39
40-43
44-46
47
48
49
50
51
52
53
54-55
56-58
59-60
61-64
65
66-68
Symbol
EXT15-EXT7
V
SS
PD15-PD0
PA11-PA0
V
DD
PA15-PA12
EA2-EA0
/EI
ER//W
/RDYE
/RES
CLK
/ROMEN
HALT
UI1-UI0
INT2-INT1
UO1-UO0
EXT3-EXT0
V
SS
EXT6-EXT4
Function
External data bus
Ground
Program data bus
Program address bus
Power Supply
Program address bus
External address bus
R/W for external bus
External bus direction
Data ready
Reset
Clock
Enable ROM
Stop execution
User inputs
Interrupts
User outputs
External data bus
Ground
External data bus
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
Direction
Input/Output
Input
Input
Output
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Output
Input/Output
Input
Input/Output
PIN FUNCTIONS
CLK
Clock
(input). External clock. The clock may be
stopped to reduce power.
EXT15-EXT0
External Data Bus
(input/output). Data bus
for user defined outside registers such as an ADC or DAC.
The pins are normally in output mode except when the
outside registers are specified as source registers in the
instructions. All the control signals exist to allow a read or
a write through this bus.
ER//W
External Bus Direction
(output, active Low). Data
direction signal for EXT-Bus. Data is available from the
CPU on EXT15-EXT0 when this signal is Low. EXT-Bus is in
input mode (high-impedance) when this signal is High.
EA2-EA0
External Address
(output). User-defined register
address output. One of eight user-defined external registers
is selected by the processor with these address pins for
read or write operations. Since the addresses are part of
the processor memory map, the processor is simply
executing internal reads and writes.
/EI
Enable Input
(output). Write timing signal for EXT-Bus.
Data is read by the external peripheral on the rising edge
of /EI. Data is read by the processor on the rising edge of
CLK, not /EI.
HALT
Halt State
(input). Stop Execution Control. The CPU
continuously executes NOPs and the program counter
remains at the same value when this pin is held High. This
signal must be synchronized with CLK.
INT2-INT0
Three Interrupts
(rising edge triggered). Interrupt
request 2-0. Interrupts are generated on the rising edge of
the input signal. Interrupt vectors for the interrupt service
starting address are stored in the program memory locations
0FFFH for INT0, 0FFEH for INT1 and 0FFDH for INT2.
Priority is: 2 = lowest, 0 = highest.
PA15-PA0
Program memory address bus
(output). For up
to 64K x 16 external program memory. These lines are tri-
stated during Reset Low.
4
DC 4083-00
Z
ILOG
P R E L I M I N A R Y
Z89C00
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSOR
PD15-PD0
Program Memory Data Input
(input). Instruc-
tions or data are read from the address specified by PD15-
PD0, through these pins and are executed or stored.
/RES
Reset
(input, active Low). Asynchronous reset signal.
A Low level on this pin generates an internal reset signal.
The /RES signal must be kept Low for at least one clock
cycle. The CPU pushes the contents of the PC onto the
stack and then fetches a new Program Counter (PC) value
from program memory address 0FFCH after the Reset
signal is released. RES Low tri-states the PA and PD bases.
/ROMEN
ROM Enable
(input). An active Low signal enables
the internal ROM. Program execution begins at 0000H
from the ROM. An active High input disables the ROM and
external fetches occur from address 0000H.
/RDYE
Data Ready
(input). User-supplied Data Ready
signal for data to and from external data bus. This pin
stretches the /EI and ER//W lines and maintains data on the
address bus and data bus. The ready signal is sampled
from the rising edge of the clock with appropriate setup
and hold times. The normal write cycle will continue from
the next rising clock only if ready is active.
UI1-UI0
Two Input Pins
(input). General purpose input
pins. These input pins are directly tested by the conditional
branch instructions. These are asynchronous input signals
that have no special clock synchronization requirements.
UO1-UO0
Two Output Pins
(output). General purpose
output pins. These pins reflect the inverted value of status
register bits S5 and S6. These bits may be used to output
data by writing to the status register.
ADDRESS SPACE
Program Memory.
Programs of up to 4K words can be
masked into internal ROM. Four locations are dedicated to
the vector address for the three interrupts (0FFDH-0FFFH)
and the starting address following a Reset (0FFCH). Internal
ROM is mapped from 0000H to 0FFFH, and the highest
location for program is 0FFBH. If the /ROMEN pin is held
High, the internal ROM is inactive and the processor
executes external fetches from 0000H to FFFFH. In this
case, locations FFFC-FFFF are used for vector addresses.
Internal Data RAM.
The Z89C00 has an internal 512 x
16-bit word data RAM organized as two banks of 256 x
16-bit words each, referred to as RAM0 and RAM1. Each
data RAM bank is addressed by three pointers, referred to
as Pn:0 (n = 0-2) for RAM0 and Pn:1 (n = 0-2) for RAM1. The
RAM addresses for RAM0 and RAM1 are arranged from
0-255 and 256-511, respectively. The address pointers,
which may be written to or read from, are 8-bit registers
connected to the lower byte of the internal 16-bit D-Bus
and are used to perform no overhead looping. Three
addressing modes are available to access the Data RAM:
register indirect, direct addressing, and short form direct.
These modes are discussed in detail later. The contents of
the RAM can be read or written in one machine cycle per
word without disturbing any internal registers or status
other than the RAM address pointer used for each RAM.
The contents of each RAM can be loaded simultaneously
into the X and Y inputs of the multiplier.
Registers.
The Z89C00 has 12 internal registers and up to
an additional eight external registers. The external registers
are user definable for peripherals such as A/D or D/A or to
DMA or other addressing peripherals. External registers
are accessed in one machine cycle the same as internal
registers.
DC 4083-00
5
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