K4D26323QG-GC
128M GDDR SDRAM
128Mbit GDDR SDRAM
1M x 32Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
with Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Revision 1.2
March 2005
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
Revision History
Revision 1.2 (March 04, 2005)
• Removed K4D26323QG-GC22 from the datasheet
128M GDDR SDRAM
Revision 1.1 (November 26, 2004)
• Removed -GC20 from the spec.
• Changed AC spec format
• Changed DC spec measurement condition from VDD(typ) to VDD(max)
Revision 1.0 (June 23, 2004)
• Changed tDQSCK/tAC of -GC22/25 from 0.55tCK to 0.45tCK
• Changed tDQSCK/tAC of -GC20 from 0.55tCK to 0.35tCK
Revision 0.4 (June 04, 2004)
-
Preliminary
• Removed K4D26323QG-GC40 from the spec
• Changed VDD&VDDQ of -GC20/22 from 1.8V+0.1V to 2.0V+0.1V
• Changed AC characteristics table on page 15~ 16 from number of clock-based to ns-based. Also key parameters are
changed as below
- Changed tRFC/tWR_A/tDAL of -GC20 from 23tCK/6tCK to 25tCK/7tCK/14tCK
- Changed tRFC/tWR_A/tDAL of -GC22 from 22tCK/6tCK to 23tCK/7tCK/14tCK
- Changed tRC/tRFC/tRP/tWR_A/tDAL of -GC25 from 17tCK/19tCK/5tCK/5tCK/10tCK to 18tCK/20tCK/6tCK/6tCK/12tCK
- Changed tRC/tRFC/tRP/tRCD/tRP/tWR_A/tDAL of -GC2A from 15tCK/17tCK/5tCK/5tCK/10tCK to 16tCK/18tCK/6tCK/6tCK/12tCK
- Changed tRC/tRFC/tRAS/tRP/tWR_A/tDAL of -GC33 from 13tCK/15tCK/9tCK/4tCK/4tCK to 15tCK/17tCK/10tCK/5tCK/5tCK/10tCK
• Added DC target spec
Revision 0.3 (April 22, 2004)
• Changed tCK(max) of K4D26323QG-GC22 from 10ns to 5ns
• Changed tWR of K4D26323QG-GC20 from 6tCK to 7tCK
• Changed tWR of K4D26323QG-GC22 from 6tCK to 7tCK
• Changed tWR of K4D26323QG-GC25 from 5tCK to 6tCK
• Changed tWR of K4D26323QG-GC33 from 4tCK to 5tCK
• Changed tWR of K4D26323QG-GC40 from 3tCK to 4tCK
Revision 0.2 (April 20, 2004)
• Changed tCK(max) of K4D26323QG-GC20 from 10ns to 5ns
Revision 0.1 (April 16, 2004)
• Typo corrected
Revision 0.0 (February 2, 2004) -
Target Spec
- 2 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
128M GDDR SDRAM
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 1.8V ± 0.1V power supply for device operation
• 1.8V ± 0.1V power supply for I/O interface
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 500MHz
• Maximum data rate up to 1.0Gbps/pin
ORDERING INFORMATION
Part NO.
K4D26323QG-GC25
K4D26323QG-GC2A
K4D26323QG-GC33
Max Freq.
400MHz
350MHz
300MHz
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
SSTL_18
144-Ball FBGA
Interface
Package
* K4D26323QG-VC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D26323QG is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
PIN CONFIGURATION
(Top View)
2
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
128M GDDR SDRAM
3
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
4
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
6
DQ2
DQ1
VSSQ
VSSQ
7
DQ0
VDDQ
VDD
VSS
8
DQ31
VDDQ
VDD
VSS
9
DQ29
DQ30
VSSQ
VSSQ
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
RFU
2
A7
11
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CK
A8/AP
12
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CK
CKE
13
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
MCL
VREF
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
A10
A2
A1
VSS
VDD
A11
A3
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
VSS
Thermal Thermal
VSS
VDD
A9
A4
VSS
RFU
1
A5
A6
NOTE:
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
DQS
DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
11
DQ
0
~ DQ
31
V
DD
V
SS
V
DDQ
V
SSQ
NC
MCL
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
Must Connect Low
- 4 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK*1
Input
Type
128M GDDR SDRAM
Function
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
DQS
0
for DQ
0
~ DQ
7,
DQS
1
for DQ
8
~ DQ
15,
DQS
2
for DQ
16
~ DQ
23,
DQS
3
for DQ
24
~ DQ
31.
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
7
.
Column address CA
8
is used for auto precharge.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
Must connect low
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
DQS
0
~ DQS
3
Input/Output
DM
0
~ DM
3
DQ
0
~ DQ
31
BA
0
, BA
1
A
0
~ A
11
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC/RFU
MCL
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
Must Connect Low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev 1.2(Mar. 2005)
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