KBE00F005A-D411
MCP MEMORY
MCP Specification
512Mb NAND*2 + 256Mb Mobile SDRAM*2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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KBE00F005A-D411
Document Title
MCP MEMORY
Multi-Chip Package MEMORY
512M Bit(64Mx8) Nand Flash*2 /
256M Bit (2Mx32x4Banks) Mobile SDRAM*2
Revision History
Revision No. History
0.0
Initial issue.
- 1Gb NAND Flash DDP B-Die _ Ver 0.1
- 512Mb Mobile SDRAM DDP F-Die _ Ver 1.0
<Common>
- Changed operating temperature : page 3
<NAND Flash> .... Ver 0.2
- Changed flow chart : page 16
- Finalize
Draft Date
April 06, 2005
Remark
Preliminary
1.0
June 21, 2005
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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Revision 1.0
June 2005
KBE00F005A-D411
MCP MEMORY
Multi-Chip Package MEMORY
512M Bit(64Mx8) Nand Flash*2 /
256M Bit (2Mx32x4Banks) Mobile SDRAM*2
FEATURES
<Common>
•
Operating Temperature : -25°C ~ 85°C
•
Package : 137ball FBGA Type - 10.5mmx13mm, 0.8mm pitch
<NAND>
•
Power Supply Voltage : 2.5~ 2.9V
•
Organization
- Memory Cell Array : (128M + 4096K)bit x 8 bit
- Data Register : (512 + 16)bit x 8bit
•
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
•
Page Read Operation
- Page Size : (512 + 16)Byte
- Random Access : 15µs(Max.)
- Serial Page Access : 50ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
•
Unique ID for Copyright Protection
<Mobile SDRAM>
•
Power Supply Voltage : 1.7~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• 2/CS Support.
Address configuration
Organization
16M x 32
Bank
BA0, BA1
Row
A0 - A12
Column Address
A0 - A7
GENERAL DESCRIPTION
The KBE00F005A is a Multi Chip Package Memory which combines 1Gbit Nand Flash Memory(organized with two pieces of 512Mbit
Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM)
1Gbit NAND Flash memory is organized as 128M x8 bits and 512Mbit Mobile SDRAM is organized as 4M x32 bits x4 banks
In 1Gbit NAND Flash,its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program oper-
ation can be performed in typically 200µs on the 528-byte page and an erase operation can be performed in typically 2ms on a 16K-
byte block. Data in the data register can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse rep-
etition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the
extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
This device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli-
cations requiring non-volatility.
In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The KBE00F005A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 137-ball FBGA Type.
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PIN DESCRIPTION
Pin Name
CLK
CKE
CS,CS1
RAS
CAS
WEd
A0 ~ A12
BA0 ~ BA1
DQM0 ~ DQM3
DQ0 ~ DQ31
Vdd
Vddq
Vss
Vssq
Pin Function(Mobile SDRAM)
System Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Address Input
Input/Output Data Mask
Data Input/Output
Power Supply
Data Out Power
Ground
DQ Ground
Pin Name
NC
DNU
Do Not Use
Pin Name
CE
RE
WP
WEn
ALE
CLE
R/B
IO0 ~ IO7
Vcc
Vss
MCP MEMORY
Pin Function(NAND Flash)
Chip Enable
Read Enable
Write Protection
Write Enable
Address Latch Enable
Command Latch Enable
Ready/Busy Output
Data Input/Output
Power Supply
Ground
Pin Function
No Connection
ORDERING INFORMATION
KB E
Samsung
MCP Memory(4chips)
Device Type
NAND + NAND + SDRAM+SDRAM
NOR Flash Density, Voltage,
Organization, Bank Size, Boot Block
00 = None
00 F 0 0 5 A - D 411
Access Time
411 : NAND Flash 50ns
NAND Flash 50ns
Mobile SDRAM 9ns
Mobile SDRAM 9ns
Package
D = FBGA(Lead-Free)
NAND Flash Density, Voltage, Organization
F = 512M+512M, 2.7V/2.7V, x8
UtRAM Density, Voltage, Organization
0 = None
SRAM Density, Voltage, Organization
0 = None
Version
A = 2nd Generation
SDRAM Interface, Density,
Voltage, Organization, Option
5 = M-SDR, 256M+256M, 1.8V/1.8V, x32
NOTE :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
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