P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z89135/Z89136
L
OW
-C
OST
DTAD C
ONTROLLER
FEATURES
Device
Z89135
Z89136
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
1
ROM
(KB)
24
24
RAM*
(Bytes)
256
256
I/O
Lines
47
47
Speed
(MHz)
20
20
Clock Speed of 20.48 MHz
16-Bit Digital Signal Processor (DSP)
6K Word DSP Program ROM
512 Words On-Chip DSP RAM
8-Bit A/D Converter with up to 128 kHz Sample Rate
10-Bit PWM D/A Converter (4 kHz to 64 kHz)
Three Vectored, Prioritized DSP Interrupts
Two DSP Timers to Support Different A/D and
D/A Sampling Rates
Z8 and DSP Operation in Parallel
IBM
®
PC-Based Development Tools
Developer’s Toolbox for T.A.M. Applications
24 KB of Z8 Program ROM (Z89135)
Watch-Dog Timer and Power-On Reset
Low Power STOP Mode
On-Chip Oscillator which Accepts a Crystal or External
Clock Drive
Two 8-Bit Z8 Counter Timers with 6-Bit Prescaler
Global Power-Down Mode
Low Power Consumption - 200 mW (typical)
Two Comparators with Programmable Interrupt Priority
Six Vectored, Priority Z8 Interrupts
RAM and ROM Protect
s
s
s
s
s
s
IBM is a registered trademark of International Business
Machines Corp.
GENERAL DESCRIPTION
The Z89135/136 is a fully integrated, dual processor con-
troller designed for low-cost digital telephone answering
machines. The I/O control processor is a Z8
®
MCU with 24
KB of program memory, two 8-bit counter/timers, and up to
47 I/O pins. The DSP is a 16-bit processor with a 24-bit
ALU and accumulator, 512 x 16 bits of RAM, single cycle
instructions, and 6K word program ROM plus constants
memory. The chip also contains a half-flash 8-bit A/D con-
verter with up to 128 kHz sample rate and 10-bit PWM D/A
converter. The sampling rates for the converters are pro-
grammable. The precision of the 8-bit A/D may be extend-
ed by resampling the data at a lower rate in software.
The Z8 and DSP processors are coupled by mailbox regis-
ters and an interrupt system, which allows DSP or Z8 pro-
grams to be directed by events in each other’s domain.
The Z89136 is the ROMless version of the Z89135. The
DSP is not ROMless. The DSP's program memory is al-
ways the internal ROM.
DS97TAD0300
PRELIMINARY
1-1
Zilog
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Z8 Core Processor
The Z8 is Zilog’s 8-bit MCU core with an Expanded Regis-
ter File to allow access to register-mapped peripheral and
I/O circuits. The Z8
®
MCU offers a flexible I/O scheme, an
efficient register and address space structure, and a num-
ber of ancillary features.
For applications demanding powerful I/O capabilities, the
Z89135/136 offers 47 pins dedicated to input and output.
These lines are grouped into six ports. Each port is config-
urable under software control to provide timing, status sig-
nals and parallel I/O with or without handshake.
There are four basic memory resources for the Z8 that are
available to support a wide range of configurations: Pro-
gram Memory, Register File, Data Memory, and Expanded
Register File. The Z8 core processor is characterized by
an efficient register file that allows any of 256 on-board
data and control registers to be the source and/or the des-
tination of almost any instruction. Traditional microproces-
sor accumulator bottlenecks are eliminated.
The Register File is composed of 236 bytes of general-pur-
pose registers, four I/O port register,s and 15 control and
status registers. The Expanded Register File consists of
mailbox registers, WDT mode register, DSP Control regis-
ter, Stop-Mode Recovery register, Port Configuration reg-
ister, and the control and data registers for Port 4 and Port
5.
To unburden the software from supporting the real-time
problems, such as counting/timing and data communica-
tion, the Z8 offers two on-chip counter/timers with a large
number of user selectable modes.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power op-
eration. The low power STOP Mode allows parameter in-
formation to be stored in the register file if power fails. An
external capacitor or battery retains power to the device.
DSP Coprocessor
The DSP coprocessor is a second generation, 16-bit two’s
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are ac-
complished in a single clock cycle. The processor contains
two on-chip data RAM blocks of 256 words, a 6K word pro-
gram ROM, 24-bit ALU, 16 x 16 multiplier, 24-bit Accumu-
lator, shifter, six-level stack, three vectored interrupts, and
two inputs for conditional program jumps. Each RAM block
contains a set of four pointers which may be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be simul-
taneously addressed and loaded to the multiplier for a true
single cycle scalar multiply.
Four external DSP registers are mapped into the expand-
ed register file of the Z8. Communication between the Z8
and the DSP occurs through those common registers
which form the mailbox registers.
The analog signal is generated by a 10-bit resolution Pulse
Width Modulator. The PWM output is a digital signal with
CMOS output levels. The output signal has a resolution of
1 in 1024 with a sampling rate of 16 kHz (XTAL = 20.48
MHz). The sampling rate can be changed under software
control and can be set at 4, 10, 16, and 64 kHz. The dy-
namic range of the PWM is from 0 to 4V.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
8, 16, 32, 64, or 128 kHz. (XTAL = 20.48 MHz) in order to
provide oversampling. The input signal is 4V peak to peak.
Scaling is normally
±
1.25V for the 2.5V peak to peak off-
set.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free running counters
that divide the crystal frequency to the appropriate sam-
pling of frequency.
Notes:
All signals with a preceding front slash, "/", are ac-
tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
1
DS97TAD0300
PRELIMINARY
1-3
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