K4N56163QF-GC
256M gDDR2 SDRAM
256Mbit gDDR2 SDRAM
Revision 2.0
October 2005
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 2.0 Oct. 2005
K4N56163QF-GC
Revision History
Revision
0.0
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Month
April
October
December
December
January
February
March
April
April
Year
2004
2004
2004
2004
2005
2005
2005
2005
2005
- Target Spec
- Defined Target Specification
History
256M gDDR2 SDRAM
- DC spec defined.
- Changed VDD&VDDQ of K4N56163QF-GC20/22 from 1.8V+0.1V to 2.0V+0.1V
- Changed ICC2P and ICC6 to 10mA
- Changed the DC characteristics table
- Added 50 ohm at the EMRS(1) programming table.
- Typo corrected
- Added Lead-Free part number in the datasheet.
- Removed K4N56163QF-GC20/22 from the datasheet.
- Modified Power-up and Initialization Sequence on page 22.
- Corrected typo.
- Changed speed bin organization.
(K4N56163QF-GC2A/K4N56163QF-GC33/K4N56163QF-GC36)
- 533 Speed bin changed into 550 speed bin.
- 600 speed bin is added.
- 667 speed bin changed into 700 speed bin.
- Seperated device operation and timing diagram
- Corrected typo.
- Corrected typo.
- Corrected typo.
- Merged Device operation and Timing diagram
1.8
May
2005
1.9
2.0
July
October
2005
2005
- 2 -
Rev. 2.0 Oct. 2005
K4N56163QF-GC
4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.0 FEATURES
• 1.8V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• 4 Banks operation
• Posted CAS
• Programmable CAS Letency : 4,5,6 and 7
• Programmable Additive Latency : 0, 1, 2, 3. 4 and 5
• Write Latency (WL) = Read Latency (RL) -1
• Burst Legth : 4 and 8 (Interleave/nibble sequential)
• Programmable Sequential/ Interleave Burst Mode
256M gDDR2 SDRAM
• Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
• Off-chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Refresh and Self Refresh
Average Refesh Period 7.8us at lower then T
CASE
85×C,
3.9us at 85×C < T
CASE
< 95 ×C
• 84 ball FBGA
2.0 ORDERING INFORMATION
Part NO.
K4N56163QF-GC25
K4N56163QF-GC2A*
K4N56163QF-GC33
K4N56163QF-GC36*
Max Freq.
400MHz
350MHz
300MHz
275MHz
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
SSTL
84 Ball FBGA
Interface
Package
* K4N56163QF-GC2A/36 can fully cover previous K4N56163QF-GC30/37(667/533Mbps) product.
* K4N56163QF-ZC is the Lead-Free part number.
3.0 GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM
The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 1000Mb/sec/pin for general applications. The chip is designed to comply with the follow-
ing key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a
source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 256Mb(x16) device receive 13/9/2 addressing. The 256Mb gDDR2 devices operate with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb gDDR2 devices are available in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
- 3 -
Rev. 2.0 Oct. 2005
K4N56163QF-GC
4.0 PIN CONFIGURATION
Normal Package (Top View)
1
VDD
UDQ6
VDDQ
UDQ4
VDD
LDQ6
VDDQ
LDQ4
VDDL
2
NC
VSSQ
UDQ1
VSSQ
NC
VSSQ
LDQ1
VSSQ
VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
3
VSS
UDM
VDDQ
UDQ3
VSS
LDM
VDDQ
LDQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
8
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
LDQS
VDDQ
LDQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
9
UDQS
VSSQ
UDQ0
VSSQ
LDQS
VSSQ
LDQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
256M gDDR2 SDRAM
VDDQ
UDQ7
VDDQ
UDQ5
VDDQ
LDQ7
VDDQ
LDQ5
VDD
ODT
VDD
VSS
Note : VDDL and VSSDL are power and ground for the DLL. lt is recommended that
they are isolated on the device from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
Ball Locations
: Populated Ball
+ : Depopulated Ball
A
B
C
D
E
F
Top View
(See the balls through the Package)
G
H
J
K
L
M
N
P
R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
- 4 -
Rev. 2.0 Oct. 2005
K4N56163QF-GC
5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
11.00
±
0.10
6.40
0.80
1.60
256M gDDR2 SDRAM
# A1 INDEX MARK (OPTIONAL)
9
A
B
C
D
E
F
8
7
6
5
4
3
2
1
K
L
5.60
M
N
P
R
3.20
84-
∅
0.45±
0.05
∅0.2
M A B
(0.90)
(1.80)
(6.15)
1.60
0.80
J
13.00
±
0.10
0.10MAX
H
11.00
±
0.10
#A1
13.00
±
0.10
11.20
G
0.35±
0.05
MAX.1.20
0.50±
0.05
Unit : mm
- 5 -
Rev. 2.0 Oct. 2005
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