P
RELIMINARY
P
RODUCT
S
PECIFICATION
2
Z87010/Z87L10
A
UDIO
E
NCODER
/D
ECODERS
FEATURES
Device
Z87010
Z87L10
ROM
(Kbyte)
4
4
I/O
Lines
16
16
Package
Information
44-Pin PLCC
44-Pin QFP
44-Pin QFP
s
s
s
s
s
2
Direct Interface to 8-Bit
µ
-law Telephone CODEC
I/O Bus (16-Bit Tristable Data, 3-Bit Address)
Wait State Generator
Two External Interrupts
Four Separate I/O Pins (2 Input, 2 Output)
Hardware
s
s
16-Bit DSP Processor
3.0V to 3.6V; -20
°
to +70
°
C, Z87L10
4.5V to 5.5V, -20
°
to +70
°
C, Z87010
Static Architecture
512 Word On-Chip RAM
Modified Harvard Architecture
Direct Interface to Z87000
Spreader/Despreader
Frequency
Hopping
Software
s
s
s
s
Full Duplex 32 Kbps ADPCM Encoding/Decoding
Single Tone and DTMF Signal Generation
Sidetone, Volume Control, Mute Functions
Large Phone Number Memory (21 numbers of 23 digits
each)
Master-Slave Protocol Interface to Z87000 Spreader/-
Despreader
s
s
s
s
s
GENERAL DESCRIPTION
The Z87010/Z87L10 is a second generation CMOS Digital
Signal Processor (DSP) that has been ROM-coded by
Zilog to provide full-duplex 32 Kbps, Adaptive Delta Pulse
Code Modulation (ADPCM) speech coding/decoding (CO-
DEC), and interface to the Z87000/Z87L00 Spread Spec-
trum Cordless Telephone Controller. Together the
Z87000/Z87L00 and Z87010/Z87L10 devices support the
implementation of a 900 MHz frequency-hopping spread
spectrum cordless telephone in conformance with United
States FCC regulations for unlicensed operation.
The Z87010 and Z87L10 are distinct 5V and 3.3V versions
of the ADPCM Audio Encoder/Decoder. For the sake of
brevity, all subsequent references to the Z87010 in this
document also are applicable to the Z87L10, unless spe-
cifically noted.
The Z87010’s single cycle instruction execution and Har-
vard bus structure promote efficient algorithm execution.
The processor contains a 4K word program ROM and 512
word data RAM. Six dual operand fetching. Three vectored
interrupts are complemented by a six level stack. The CO-
DEC interface enables high-speed transfer rate to accom-
modate digital audio and voice data. A dedicated
Counter/Timer provides the necessary timing signals for
the CODEC interface. An additional 13-bit timer is dedicat-
ed for general-purpose use.
The Z87010’s circuitry is optimized to accommodate intri-
cate signal processing algorithms and is used here for
speech compression/decompression, generation of DTMF
tones and other cordless telephone functions. Dedicated
hardware allows direct interface to a variety of CODEC
DS96WRL0601
PRELIMINARY
2-1
Z87010/Z87L10
Audio Encoder/Decoders
Zilog
GENERAL DESCRIPTION
(Continued)
ICs. As configured by the Zilog-provided embedded soft-
ware for digital cordless phones, the Z87010 supports a
low-cost 8-bit
µ
-law telephone CODEC. The Z87010 is to
be used with the Z87000 and operates at 16.384 MHz, pro-
viding 16 MIPS of processing power needed for the cord-
less telephone application.
RXD
256 Word
RAM0
EXT 0-15
/RDYE
ER//W
/EI
EA0-2
Wait
State
Generator
13-Bit
Timer
Power
4K Words
Program ROM
16-Bit
I/O
Interface
256 Word
RAM1
Dual
CODEC
Interface
TXD
SCLK
FS0
FS1
DSP
Core
UO0-1
UI0-1
/RESET
/INT0-2
VDD
VSS
Figure 1. Z87010 Functional Block Diagram
Notes:
All signals with a preceding front slash, ‘/’, are
active Low, e.g., B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
2-2
PRELIMINARY
DS96WRL0601
Power technology
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