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CY27C256A-90ZC

Description
OTP ROM, 32KX8, 90ns, CMOS, PDSO28, TSOP-28
Categorystorage    storage   
File Size169KB,9 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY27C256A-90ZC Overview

OTP ROM, 32KX8, 90ns, CMOS, PDSO28, TSOP-28

CY27C256A-90ZC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeTSOP
package instructionTSOP-28
Contacts28
Reach Compliance Codenot_compliant
ECCN codeEAR99
Factory Lead Time1 week
Maximum access time90 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G28
JESD-609 codee0
memory density262144 bit
Memory IC TypeOTP ROM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeTSSOP28,.53,22
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Programming voltage12.75 V
Certification statusNot Qualified
Maximum standby current0.015 A
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.55 mm
Terminal locationDUAL
fax id: 3026
CY27C256A
1-Megabit (32K x 8) CMOS EPROM
Features
Very fast read access time: (45−200 ns)
5V ± 10% power supply
Capable of withstanding >2001V ESD
Latch-up protection up to 200 mA
Two line control functions to prevent bus contention
Standard JEDEC packages
— 32-pin PLCC
— 28-pin TSOP
— 28-pin, 600-mil plastic DIP
— 32-pin, hermetic LCC
— 28-pin, 600-mil hermetic DIP
• Available in commercial, industrial, and military
temperature ranges
windowed packages (28-pin hermetic DIP and 32-pin LCC)
which allow the device to be erased with UV light for 100%
reprogrammability.
The CY27C256A is equipped with a power-down chip enable
(CE) input and output enable (OE) to prevent bus contention.
When CE is deasserted, the device powers down to a
low-power stand-by mode. The OE pin three-states the out-
puts without putting the device into stand-by mode. While CE
offers lower power, OE provides a more rapid transition to and
from three-stated outputs.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The EPROM cell requires only 12.75V for the supervoltage
and low programming current allows for gang programming.
The device allows for each memory location to be tested
100%, because each location is written to, erased, and
repeatedly exercised prior to encapsulation. Each device is
also tested for AC performance to guarantee that the product
will meet DC and AC specification limits after customer
programming.
The CY27C256A is read by asserting both the CE and the OE
inputs. The contents of the memory location selected by the
address on inputs A
14
–A
0
will appear at the outputs O
7
−O
0
.
Functional Description
The CY27C256A is a high-performance, 256-Kbit ultraviolet
erasable programmable read-only memory (EPROM) orga-
nized as 32 Kbytes by 8 bits. It is available in JEDEC-standard,
one-time programmable (OTP), 32-pin PLCC and 28-pin PDIP
and TSOP packages. The CY27C256A is also available in
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
PROGRAMMABLE
ARRAY
O0
O1
O2
MULTIPLEXER
O3
ADDRESS INPUTS
A7
A8
A9
A10
A11
A12
A13
A14
DATA OUTPUTS
O4
O5
ADDRESS
DECODER
POWER DOWN
O6
O7
CE
OE
OUTPUT ENABLE
DECODER
C256A–1
Cypress Semiconductor Corporation
3901 North First Street
San Jose •
CA 95134 •
408-943-2600
April 1995 - Revised November 10, 1997

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