AD9575-EVALZ-LVD datasheet, PDF

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AD9575-EVALZ-LVD: DescriptionNetwork Clock Generator, Two Outputs; File Size327KB，16 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Network Clock Generator, Two Outputs

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Network Clock Generator, Two Outputs

AD9575

FEATURES

Fully integrated VCO/PLL core

0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz

0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz

0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz

Input crystal frequency of 19.44 MHz, 25 MHz, or

25.78125 MHz

Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,

100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,

159.375 MHz, 161.13 MHz, and 312.5 MHz outputs

LVDS/LVPECL/LVCMOS output format

Integrated loop filter

Space saving 4.4 mm × 5.0 mm TSSOP

100 mA power supply current (LVDS output)

120 mA power supply current (LVPECL output)

3.3 V operation

GENERAL DESCRIPTION

The AD9575 provides a highly integrated, dual output clock

generator function including an on-chip PLL core that is

optimized for network clocking. The integer-N PLL design is

based on the Analog Devices, Inc., proven portfolio of high

performance, low jitter frequency synthesizers to maximize line

card performance. Other applications with demanding phase

noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency detector

(PFD), a precision charge pump (CP), a low phase noise voltage

controlled oscillator (VCO), and pin selectable feedback and

output dividers.

By connecting an external crystal, popular network output fre-

quencies can be locked to the input reference. The output divider

and feedback divider ratios are pin programmable for the required

output rates. No external loop filter components are required,

thus conserving valuable design time and board space.

The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP

and can be operated from a single 3.3 V supply. The temperature

range is −40°C to +85°C.

APPLICATIONS

GbE/FC/SONET line cards, switches, and routers

CPU/PCI-E applications

Low jitter, low phase noise clock generation

FUNCTIONAL BLOCK DIAGRAM

VDD × 5

LVDS OR

LVPECL

DIVIDERS

LDO

THIRD-ORDER

LPF

PFD/CP

XTAL

OSC

VCO

100MHz

TO 312.5MHz

LVCMOS

33.33MHz/

62.5MHz/SEL1

SEL

08462-001

AD9575

GND × 5

SEL0

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

AD9575

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter (Typ/Max)........................................ 4

LVPECL Clock Output Jitter (Typ/Max)................................... 4

Output Frequency Select ............................................................. 5

Clock Outputs ............................................................................... 5

Timing Characteristics ................................................................ 5

Power .............................................................................................. 6

Crystal Oscillator .......................................................................... 6

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings ............................................................7

Thermal Resistance .......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics ..............................................9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump............ 12

Power Supply............................................................................... 12

LVPECL Clock Distribution ..................................................... 12

LVDS Clock Distribution .......................................................... 13

LVCMOS Clock Distribution ................................................... 13

Typical Application Circuit ....................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

REVISION HISTORY

3/10—Rev.

0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Table 1, Table 2, and Table 3 ....................................... 4

Changes to Table 4 and Table 6 ....................................................... 5

Changes to Table 7 and Table 8 ....................................................... 6

Changes to Table 12 .......................................................................... 8

Added Figure 11; Renumbered Figures Sequentially ................ 10

Changes to Figure 13 ...................................................................... 10

Changes to Theory of Operation Section and Figure 19........... 12

Changes to Figure 24 ...................................................................... 13

1/10—Revision 0: Initial Version

Rev. A | Page 2 of 16

AD9575-EVALZ-LVD Related Products

	AD9575-EVALZ-LVD	AD9575	AD9575-EVALZ-PEC
Description	Network Clock Generator, Two Outputs	Network Clock Generator, Two Outputs	Network Clock Generator, Two Outputs

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