Network Clock Generator, Two Outputs
AD9575
FEATURES
Fully integrated VCO/PLL core
0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz
0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz
0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz
Input crystal frequency of 19.44 MHz, 25 MHz, or
25.78125 MHz
Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,
100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,
159.375 MHz, 161.13 MHz, and 312.5 MHz outputs
LVDS/LVPECL/LVCMOS output format
Integrated loop filter
Space saving 4.4 mm × 5.0 mm TSSOP
100 mA power supply current (LVDS output)
120 mA power supply current (LVPECL output)
3.3 V operation
GENERAL DESCRIPTION
The AD9575 provides a highly integrated, dual output clock
generator function including an on-chip PLL core that is
optimized for network clocking. The integer-N PLL design is
based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize line
card performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.
The PLL section consists of a low noise phase frequency detector
(PFD), a precision charge pump (CP), a low phase noise voltage
controlled oscillator (VCO), and pin selectable feedback and
output dividers.
By connecting an external crystal, popular network output fre-
quencies can be locked to the input reference. The output divider
and feedback divider ratios are pin programmable for the required
output rates. No external loop filter components are required,
thus conserving valuable design time and board space.
The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP
and can be operated from a single 3.3 V supply. The temperature
range is −40°C to +85°C.
APPLICATIONS
GbE/FC/SONET line cards, switches, and routers
CPU/PCI-E applications
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
VDD × 5
LVDS OR
LVPECL
DIVIDERS
LDO
THIRD-ORDER
LPF
PFD/CP
XTAL
OSC
VCO
100MHz
TO 312.5MHz
LVCMOS
33.33MHz/
62.5MHz/SEL1
SEL
08462-001
AD9575
GND × 5
SEL0
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9575
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
PLL Characteristics ...................................................................... 3
LVDS Clock Output Jitter (Typ/Max)........................................ 4
LVPECL Clock Output Jitter (Typ/Max)................................... 4
Output Frequency Select ............................................................. 5
Clock Outputs ............................................................................... 5
Timing Characteristics ................................................................ 5
Power .............................................................................................. 6
Crystal Oscillator .......................................................................... 6
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings ............................................................7
Thermal Resistance .......................................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
Phase Frequency Detector (PFD) and Charge Pump............ 12
Power Supply............................................................................... 12
LVPECL Clock Distribution ..................................................... 12
LVDS Clock Distribution .......................................................... 13
LVCMOS Clock Distribution ................................................... 13
Typical Application Circuit ....................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
3/10—Rev.
0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 1, Table 2, and Table 3 ....................................... 4
Changes to Table 4 and Table 6 ....................................................... 5
Changes to Table 7 and Table 8 ....................................................... 6
Changes to Table 12 .......................................................................... 8
Added Figure 11; Renumbered Figures Sequentially ................ 10
Changes to Figure 13 ...................................................................... 10
Changes to Theory of Operation Section and Figure 19........... 12
Changes to Figure 24 ...................................................................... 13
1/10—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD9575
SPECIFICATIONS
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
given over the full V
S
and T
A
(−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter
PHASE NOISE CHARACTERISTICS
PLL Noise (100 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (106.25 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (125 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (155.52 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (156.25 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (159.375 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
Min
LVDS
Typ
Max
Min
LVCMOS
Typ
Max
Min
LVPECL
Typ
Max
Unit
−123
−128
−131
−150
−156
−156
−121
−127
−130
−149
−156
−156
−120
−126
−128
−148
−155
−156
−118
−123
−125
−147
−155
−156
−118
−124
−126
−146
−155
−155
−118
−124
−126
−146
−155
−155
−122
−129
−131
−151
−158
−158
−121
−128
−130
−150
−158
−159
−120
−127
−129
−150
−157
−158
−118
−123
−125
−149
−157
−157
−118
−125
−127
−148
−157
−157
−118
−125
−126
−147
−156
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 3 of 16
AD9575
Parameter
PLL Noise (161.132812 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (312.5 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (33.33 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 5 MHz
PLL Noise (62.5 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 5 MHz
Spurious Content
PLL Figure of Merit
Min
LVDS
Typ
−118
−122
−126
−144
−154
−155
−112
−119
−120
−140
−152
−153
−131
−138
−140
−155
−155
−126
−133
−134
−150
−152
−70
−217
−70
−217
Max
Min
LVCMOS
Typ
Max
Min
LVPECL
Typ
Max
−119
−123
−126
−146
−156
−156
−112
−119
−120
−142
−154
−155
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc/Hz
LVDS CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 2.
Jitter Integration
Bandwidth
12 kHz to 20 MHz
1.875 MHz to 20 MHz
637 kHz to 10 MHz
100
MHz
0.38/0.50
106.25
MHz
0.40/0.54
0.15/0.21
125
MHz
0.37/0.47
155.52
MHz
0.41/0.54
156.25
MHz
0.39/0.51
0.15/0.27
159.375
MHz
0.38/0.51
161.13
MHz
0.44/0.61
312.5
MHz
0.36/0.48
Unit
ps rms
ps rms
ps rms
LVPECL CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 3.
Jitter Integration
Bandwidth
12 kHz to 20 MHz
1.875 MHz to 20 MHz
637 kHz to 10 MHz
100
MHz
0.36/0.46
106.25
MHz
0.44/0.68
0.22/0.35
125
MHz
0.36/0.45
155.52
MHz
0.40/0.52
156.25
MHz
0.39/0.64
0.19/0.54
159.375
MHz
0.41/0.62
161.13
MHz
0.43/0.69
312.5
MHz
0.38/0.49
Unit
ps rms
ps rms
ps rms
Rev. A | Page 4 of 16
AD9575
OUTPUT FREQUENCY SELECT
Minimum (min) and maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 4.
Parameter
Select Pins (SEL0/SEL1)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Min
0.83 × V
S
+ 0.2
0.33 × V
S
− 0.2
190
150
Typ
Max
Unit
V
V
μA
μA
Test Conditions/Comments
Pull-up to V
S
Pull-down to GND
CLOCK OUTPUTS
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 5.
Parameter
LVDS CLOCK OUTPUT
Output Frequency
Differential Output Voltage (V
OD
)
Delta V
OD
Output Offset Voltage (V
OS
)
Delta V
OS
Short-Circuit Current (I
SA
, I
SB
)
Duty Cycle
LVPECL CLOCK OUTPUT
Output Frequency
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Differential Output Voltage (V
OD
)
Duty Cycle
LVCMOS CLOCK OUTPUT
Output Frequency
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Duty Cycle
Min
Typ
Max
312.5
450
25
1.375
25
24
55
312.5
V
S
− 0.8
V
S
− 1.7
800
55
62.5
V
S
− 0.1
45
50
0.1
55
Unit
MHz
mV
mV
V
mV
mA
%
MHz
V
V
mV
%
MHz
V
V
%
Test Conditions/Comments
Termination = 100 Ω differential; default
See Figure 2 for definition
250
1.125
340
1.25
14
50
Output shorted to GND
45
V
S
− 1.5
V
S
− 2.5
430
45
V
S
− 1.05
V
S
− 1.75
640
50
See Figure 2 for definition
TIMING CHARACTERISTICS
Table 6.
Parameter
LVDS
Output Rise Time, t
RL
Output Fall Time, t
FL
LVPECL
Output Rise Time, t
RL
Output Fall Time, t
FL
LVCMOS
Output Rise Time, t
RC
Output Fall Time, t
FC
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 100 Ω differential; C
LOAD
= 0 pF;
C
AC
= 0.1 μF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 200 Ω to GND; C
LOAD
= 0 pF;
C
AC
= 0.1 μF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 50 Ω to 0 V; C
LOAD
= 5 pF;
C
AC
= 0.1 μF
20% to 80%
80% to 20%
150
150
200
200
300
300
ps
ps
180
180
250
250
300
300
ps
ps
0.50
0.50
0.70
0.70
1.10
1.10
ns
ns
Rev. A | Page 5 of 16
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