P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86129/130/131
NTSC L
INE
21 D
ECODER
FEATURES
Speed
(MHz)
12
12
12
Pin Count/
Package Types
18-Pin DIP, SOIC
18-Pin DIP, SOIC
18-Pin DIP, SOIC
Standard
Temp. Range
0
°
to +70
°
C
0
°
to +70
°
C
0
°
to +70
°
C
s
1
Devices
Z86129
Z86130
Z86131
s
On-Screen Display
& Closed Captioning
Yes
No
No
Automatic Data Extraction
V-Chip
Time of Day
Yes
Yes
No
Yes
Yes
Yes
Complete Stand-Alone Line 21 Decoder for Closed-
Captions and Extended Data Services (XDS).
Preprogrammed to Provide Full Compliance with EIA-
608 Specifications for Extended Data Services.
Automatic Extraction and Serial Output of Special
XDS Packets such as Time of Day, Local Time Zone,
and Program Rating (
V-Chip
).
Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows.
Minimal Communications and Control Overhead
Provides Simple Implementation of Violence Block,
Closed Caption, and Auto Clock Set Features.
Programmable, Full Screen On-Screen Display (OSD)
for Creating OSD or Captions inside a Picture-in-
Picture (PiP) Window (Z86129 only).
I
2
C Serial Data and Control Communication
User-Programmable Horizontal Display Position for
easy OSD Centering and Adjustment (Z86129 only).
s
s
s
s
s
s
GENERAL DESCRIPTION
The Z86129/130/131 is a stand-alone integrated circuit,
capable of processing Vertical Blanking Interval (VBI) data
from both fields of the video frame in data conforming to
the transmission format defined in the Television Decoder
Circuits Act of 1990 and in accordance with the Electronics
Industry Association specification 608 (EIA-608).
The Line 21 data stream can consist of data from several
data channels multiplexed together. Field 1 has four data
channels, two Captions and two Text. Field 2 has five
additional data channels, two Captions, two Text and
Extended Data Services (XDS). XDS data structure is
defined in EIA-608. The Z86129 can recover and display
data transmitted on any of these nine data channels. The
Z86130 and Z86131 are derivatives of the Z86129 which
can recover XDS data and output the recovered data via
the serial port. The Z86130 and Z86131 do not have OSD
capability, but are ideally suited for Line 21 data slicer
applications.
The Z86129/130/131 can recover and output to a host
processor via the I
2
C serial bus any XDS data packet
defined in EIA-608. On-chip XDS filters are fully
programmable, enabling recovery of only those XDS data
packets selected by the user, making the Z86129/130 an
ideal choice for implementing NTSC Violence Block. The
Z86131 is designed especially for extracting XDS time
information for Automatic Clock-Set features in TVs,
VCRs, and Set-Top boxes.
In addition, the Z86129/130 is ideally suited to monitor Line
21 of video displayed in a PiP window for violence blocking
purposes. A block diagram of the Z86129/130/131 is
shown in Figure 1.
DS96TEL0200
1
PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
PIN DESCRIPTION
Table 1. 18-Pin DIP and SOIC Pin Identification
V
SS
GREEN*
BLUE*
SEN
HIN
SMS
VIDEO
CSYNC
LPF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RED*
No. Symbol
BOX*
SDO
SCK
SDA
VIN/INTRO
V
DD
V
SS
(A)
RREF
Function
Power Supply GND
Video Output
Video Output
Serial Enable
Horizontal In
Serial Mode Select
Composite Video
Composite Sync
Loop Filter
Resistor Reference
Pwr. Supply (Analog) GND
Power Supply
Vertical In/Interrupt Out
Serial Data
Serial Clock
Serial Data Out
OSD Timing Signal
Video Output
Direction
Output
Output
Input
Input
Input
Input
Output
Output
Input
1
1
2*
3*
4
5
6
7
8
9
10
11
13
14
15
16
17*
18*
V
SS
GREEN
BLUE
SEN
HIN
SMS
VIDEO
CSYNC
LPF
RREF
V
SS
(A)
VIN/INTRO
SDA
SCK
SDO
BOX
RED
*Z86129 Only
Figure 2. Z86129/130/131, 18-Pin DIP/SOIC
Pin Configuration
12 V
DD
In/Output
In/Output
Input
Output
Output
Output
Note:
DIP and SOIC pin configuration are identical. *However,
the Z86130/Z86131 do not have signals on pins 2, 3, 18 and 19.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
IN
V
OUT
I
IN
I
OUT
I
DD
P
D
T
STG
T
L
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CAUTION:
DC Input Current per Pin
DC Output Current per Pin
DC Supply Current
Power Dissipation per Device
Storage Temperature
Lead Temperature, 1 mm from Case for 10 seconds
Value
–0.5 to 6.0
–0.5 to V
DD
+0.5
–0.5 to V
DD
+0.5
+10
+20
+30
300
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°
C
°
C
Notes:
Voltages referenced to V
SS
(A) and V
SS
.
Maximum ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.
DS96TEL0200
3
PRELIMINARY
Z86129/130/131
NTSC Line 21 Decoder
ELECTRICAL CHARACTERISTICS
Non Standard Video Signals must have the following characteristics:
Parameter
Sync Amplitude
Vertical Pulse Width
Vertical Pulse Tilt
H Timing
Conditions
200 mV minimum
3H
±
0.5H
20 mV maximum
Phase Step (Head Switch)
±
10
µ
s maximum
Fh Deviation (long term)
±
0.5% maximum
Fh p-p Deviation (short term)
±
0.3% maximum
The internal sync circuits will lock to all 525 or 625 line signals having a vertical
sync pulse that meets the following conditions:
1. It is at least 2H wide.
2. It starts at the proper 2H boundary for its field.
3. If equalizing pulse serrations are present, they must be less than 0.125H in
width.
The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR
weighted) with one error per row or better at that level.
Input
1
Vertical Sync Signal
Minimum Signal-to-Noise
Ratio to Composite Video
Horizontal Signal Input (preferably H Flyback)
Parameter
Amplitude
Video Lock Mode:
HIN Lock Mode:
Conditions
CMOS level signal where Low <= 0.2 V
CC
Polarity
Frequency
Polarity
Frequency
Any
15,734.263 Hz
±
3%
Any
Same as Display Horizontal Flyback Pulse (HFB) pulse
Line 21 Input Parameters (at 1.0V p-p)
Note:
Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
Parameter
Cod Amplitude
Code Zero Level
Start of Code
Start of Data
Conditions
50 IRE
5 IRE, +15 IRE relative to Back Porch
10.5
±0.5 µs,
(Measured from the midpoint of the falling edge of the last clock run-in cycle
to the midpoint of the rising edge of the start bit.)
3.972
µs,
–0.00
µsec,
+0.30
µs
(Measured from the midpoint of the falling edge of the last
clock run-in cycle to the midpoint of the rising edge of the start bit.
Timing Signals
Parameter
Dot
Dot Period
Character Cell Width
Width of Row (Box)
Width of Row (Char)
Horizontal Display Timing
Conditions
768 x FH = 12.0839 MHz
82.75 ns
1.324
µs
(tH/48)
45.018
µs
(34 chars = 17/24 x tH
42.370
µs
(32 chars = 2/3 x tH
The timing of the output signals Box and RGB have been set to make a centered display.
The positioning of these outputs can be adjusted in 330 ns increments by writing a new
value to the Z86129 H Position Register (Address = 02h).
5
DS96TEL0200
RF/Wirelessly
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