quadrant multiplying, digital-to-analog converter with
input data latches. The input data is loaded into the
DAC as a 12-bit data word. The data flows through to
the DAC when both the chip select (CS) and the write
(WR) pins are at a logic low.
Laser-trimmed thin-film resistors and excellent CMOS
voltage switches provide true 12-bit integral and dif-
ferential linearity. The device operates on a single
+5V to +15V supply and is available in 20-pin plastic
DIP or 20-lead plastic SOIC packages. Devices are
specified over the commercial.
The DAC7545 is well suited for battery or other low
power applications because the power dissipation is
less than 0.5mW when used with CMOS logic inputs
and V
DD
= +5V.
R
FB
20
1
V
REF
19
12-Bit
Multiplying DAC
2
OUT 1
AGND
12
WR 17
CS 16
Input
Data Latches
12
DB
11
-DB
0
(Pins 4-15)
18
3
V
DD
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) Temperature ranges—J, K, L, GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Guaranteed but not tested. (4) DB
0
-DB
11
= 0V
to V
DD
or V
DD
to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure
compliance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
DAC7545
2
ABSOLUTE MAXIMUM RATINGS
(1)
T
A
= +25°C, unless otherwise noted.
V
DD
to DGND ........................................................................... –0.3V, +17
Digital Input to DGND ............................................................... –0.3V, V
DD
V
RFB
, V
REF
, to DGND ........................................................................
±25V
V
PIN 1
to DGND ......................................................................... –0.3V, V
DD
AGND to DGND ........................................................................ –0.3V, V
DD
Power Dissipation: Any Package to +75°C .................................... 450mW
Derates above +75°C by ................................ 6mW/°C
Operating Temperature:
Commercial J, K, L, GL .................................................. –40°C to +85°C
Storage Temperature ...................................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
NOTE: (1) Stresses above those listed above may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
PIN CONNECTIONS
Top View
DIP/SOIC
OUT 1
AGND
DGND
(MSB) DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
1
2
3
4
5
6
7
8
9
DAC7545
20 R
FB
19 V
REF
18 V
DD
17 WR
16 CS
15 DB
0
(LSB)
14 DB
1
13 DB
2
12 DB
3
11 DB
4
DB
5
10
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integral circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ORDERING INFORMATION
PRODUCT
DAC7545JP
DAC7545KP
DAC7545LP
DAC7545GLP
DAC7545JU
DAC7545KU
DAC7545LU
DAC7545GLU
PACKAGE
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Plastic SOIC
Plastic SOIC
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
PACKAGE INFORMATION
PRODUCT
DAC7545JP
DAC7545KP
DAC7545LP
DAC7545GLP
DAC7545JU
DAC7545KU
DAC7545LU
DAC7545GLU
PACKAGE
20-Pin PDIP
20-Pin PDIP
20-Pin PDIP
20-Pin PDIP
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
PACKAGE DRAWING
NUMBER
(1)
222
222
222
222
221
221
221
221
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
RELATIVE
ACCURACY (LSB)
±2
±1
±1/2
±1/2
±2
±1
±1/2
±1/2
GAIN ERROR (LSB)
V
DD
= +5V
±20
±10
±5
±2
±20
±10
±5
±2
3
DAC7545
WRITE CYCLE TIMING DIAGRAM
CS
t
CS
t
CH
V
DD
0
WR
t
WR
V
DD
t
DH
0
V
DD
0
Write Mode
CS and WR low, DAC responds
to Data Bus (DB
0
-DB
11
) inputs.
Mode Selection
Hold Mode
Either CS or WR high, data bus
(DB
0
-DB
11
) is locked out; DAC
holds last data present when
WR or CS assumed high state.
t
DS
Data In
(DB
0
-DB
11
)
V
IH
V
IL
Data
Valid
NOTES: V
DD
= +5V, t
R
= t
F
= 20ns. V
DD
= +15V, t
R
= t
F
= 40ns. All inputs signal
rise and fall times measured from 10% to 90% of V
DD
. Timing measurement
reference level is (V
IH
+ V
IL
)/2.
23
22
PAD
1
2
3
4
5
6
7
8
9
10
11
12
FUNCTION
OUT 1
AGND
AGND
DGND
DB11
DB10
DB9
DB8
DB7
DB6
DB
5
DB
4
PAD
13
14
15
16
17
18
19
20
21
22
23
FUNCTION
DB
3
DB
2
DB
1
(LSB)
DB
0
CS
WR
XYR
V
DD
V
REF
R
FB
OUT
1
Substrate Bias:
Isolated. NC: No Connection
MECHANICAL INFORMATION
MILS (0.001")
Die Size
Die Thickness
Min. Pad Size
136 x 134
±5
20
±3
4x4
MILLIMETERS
3.45 x 3.40
±0.13
0.51
±0.08
0.10 x 0.10
Aluminum
DAC7545 DIE TOPOGRAPHY
Metalization
DISCUSSION
OF SPECIFICATIONS
Relative Accuracy
This term (also known as end point linearity) describes the
transfer function of analog output to digital input code.
Relative accuracy describes the deviation from a straight
line after zero and full scale have been adjusted.
Differential Nonlinearity
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output, for adjacent input code changes. A
differential nonlinearity specification of 1LSB guarantees
monotonicity.
Gain Error
Gain error is the difference in measure of full-scale output
versus the ideal DAC output. The ideal output for the
DAC7545 is –(4095/4096)(V
REF
). Gain error may be ad-
justed to zero using external trims as shown in the applica-
tions section.
Output Leakage Current
The current which appears at OUT 1 with the DAC loaded
with all zeros.
Multiplying Feedthrough Error
The AC output error due to capacitive feedthrough from
V
REF
to OUT 1 with the DAC loaded with all zeros. This test
is performed using a 10kHz sine wave.
Output Current Settling Time
The time required for the output to settle within
±0.5LSB
of final value from a change in code of all zeros to all ones,
or all ones to all zeros.
DAC7545
4
Propagation Delay
The delay of the internal circuitry is measured as the time
from a digital code change to the point at which the
output reaches 90% of final value.
Digital-to-Analog Glitch Impulse
The area of the glitch energy measured in nanovolt-seconds.
Key contributions to glitch energy are internal circuitry
timing differences and charge injected from digital
logic. The measurement is performed with V
REF
= GND and
an OPA600 as the output op amp and G
1
(phase
compensation) = 0pF.
Monotonicity
Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC7545 is guaranteed monotonic to 12 bits, except the
J grade is specified to be 10-bit monotonic.
Power Supply Rejection
Power supply rejection is the measure of the sensitivity of
the output (full scale) to a change in the power supply
voltage.
current than normal. Minimizing this transition time through
the linear region and insuring that the digital inputs are
operated as close to the rails as possible will minimize the
supply drain current.
APPLICATIONS
UNIPOLAR OPERATION
Figure 2 shows the DAC7545 connected for unipolar opera-
tion. The high-grade DAC7545 is specified for a 1LSB gain
error, so gain adjust is typically not needed. However, the
resistors shown are for adjusting full-scale errors. The value
of R
1
should be minimized to reduce the effects of mis-
matching temperature coefficients between the internal and
external resistors. A range of adjustment of 1.5 times the
desired range will be adequate. For example, for a
DAC7545JP, the gain error is specified to be
±25LSB.
A
range of adjustment of
±37LSB
will be adequate. The
equation below results in a value of 458Ω for the potentiom-
eter (use 500Ω).
R
1
=
R
LADDER
(3
x
Gain Error)
4096
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of the digital-to-
analog converter portion of the DAC7545. The current from
the V
REF
pin is switched from OUT 1 to AGND by the
FET switch. This circuit architecture keeps the resistance at
the reference pin constant and equal to R
LDR
, so the reference
could be provided by either a voltage or current, AC or DC,
positive or negative polarity, and have a voltage range up to
±20V
even with V
DD
= 5V. The R
LDR
is equal to “R” and is
typically 11kΩ.
V
REF
R
R
R
R
The addition of R
1
will cause a negative gain error. To
compensate for this error, R
2
must be added. The value of R
2
should be one-third the value of R
1
.
The capacitor across the feedback resistor is used to com-
pensate for the phase shift due to stray capacitances of the
circuit board, the DAC output capacitance, and op amp input
capacitance. Eliminating this capacitor will result in exces-
sive ringing and an increase in glitch energy. This capacitor
should be as small as possible to minimize settling time.
The circuit of Figure 2 may be used with input voltages up
to
±20V
as long as the output amplifier is biased to handle
the excursions. Table I represents the analog output for four
codes into the DAC for Figure 2.
+5V
R
2
C
1
33pF
OUT 1
AGND
DGND
V
OUT
OPA604
2R
2R
2R
2R
2R
R
FB
V
IN
V
DD
V
REF
R
1
R
FB
OUT 1
DAC7545
AGND
DB11
(MSB)
DB10
DB9
DB0
(LSB)
DB
0
-DB
11
FIGURE 1. Simplified DAC Circuit of the DAC7545.
The output capacitance of the DAC7545 is code dependent
and varies from a minimum value (70pF) at code 000H to a
maximum (200pF) at code FFFH.
The input buffers are CMOS inverters, designed so that
when the DAC7545 is operated from a 5V supply (V
DD
), the
logic threshold is TTL-compatible. Being simple CMOS
inverters, there is a range of operation where the inverters
operate in the linear region and thus draw more supply
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