MT4VDDT3264HG-40BF2 datasheet, PDF

128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM

Features

DDR SDRAM SODIMM

MT4VDDT1664H – 128MB

MT4VDDT3264H – 256MB

For component data sheets, refer to Micron’s Web site:

www.micron.com

Features

• 200-pin, small-outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC2100, PC2700, or PC3200

• 128MB (16 Meg x 64) or 256MB (32 Meg x 64)

• Vdd = Vddq = +2.5V (-40B: Vdd = Vddq = +2.6V)

• Vddspd = +2.3V to +3.6V

• 2.5V I/O (SSTL_2-compatible)

• Internal, pipelined double data rate (DDR)

2n-prefetch

architecture

• Bidirectional data strobe (DQS) transmitted/

received with data—that is, source-synchronous

data capture

• Differential clock inputs (CK and CK#)

• Multiple internal device banks for concurrent

operation

• Single rank

• Selectable burst lengths (BL): 2, 4, or 8

• Auto precharge option

• Auto refresh and self refresh modes: 7.8125µs

maximum average periodic refresh interval

• Serial presence-detect (SPD) with EEPROM

• Selectable CAS latency (CL) for maximum

compatibility

• Gold edge contacts

Figure 1:

200-Pin SODIMM (MO-224)

PCB height: 31.75mm (1.25in)

Options

• Operating temperature

–

Commercial (0°C

≤

T

A

≤

+70°C)

–

Industrial (–40°C

≤

T

A

≤

+85°C)

• Package

–

200-pin DIMM (standard)

–

200-pin DIMM (Pb-free)

• Memory clock, speed, CAS latency

–

5ns (200 MHz), 400 MT/s, CL = 3

–

6ns (167 MHz), 333 MT/s, CL = 2.5

–

7.5ns (133 MHz), 266 MT/s, CL = 2

2

–

7.5ns (133 MHz), 266 MT/s, CL = 2.5

2

1

Marking

None

I

G

Y

-40B

-335

-26A

-265

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. Not recommended for new designs.

Table 1:

Speed

Grade

-40B

-335

-26A

-265

Key Timing Parameters

Data Rate (MT/s)

Industry

Nomenclature

PC3200

PC2700

PC2100

Notes:

CL = 3

400

–

CL = 2.5

333

266

CL = 2

266

200

t

RCD

t

RP

t

RC

(ns)

15

18

20

(ns)

15

18

20

(ns)

55

60

65

Notes

1

1. The values of

t

RCD and

t

RP for -335 modules show 18ns to align with industry specifications;

actual DDR SDRAM device specifications are 15ns.

PDF: 09005aef837131bb/Source: 09005aef8086ea0b

dd4c16_32x64h.fm - Rev. E 10/08 EN

1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM

Features

Table 2:

Parameter

Refresh count

Row address

Device bank address

Device configuration

Column

address

Module rank address

Addressing

128MB

8K

8K (A0–A12)

4 (BA0, BA1)

256Mb (16 Meg x 16)

512 (A0–A8)

1 (S0#)

256MB

8K

8K (A0–A12)

4 (BA0, BA1)

512Mb (32 Meg x 16)

1K (A0–A9)

1 (S0#)

Table 3:

Part Numbers and Timing Parameters – 128MB Modules

Base device: MT46V16M16,

1

256Mb DDR SDRAM

Module

Density

128MB

Module

Bandwidth

3.2 GB/s

2.7 GB/s

2.1 GB/s

Memory Clock/

Data Rate

5ns/400 MT/s

6ns/333 MT/s

7.5ns/266 MT/s

Clock Latency

(CL-

t

RCD-

t

RP)

3-3-3

2.5-3-3

2-3-3

2.5-3-3

Part Number

2

Configuration

16 Meg x 64

MT4VDDT1664HG-40B__

MT4VDDT1664HY-40B__

MT4VDDT1664HG-335__

MT4VDDT1664HY-335__

MT4VDDT1664HG-26A__

MT4VDDT1664HG-265__

MT4VDDT1664HY-265__

Table 4:

Part Numbers and Timing Parameters – 256MB Modules

Base device: MT46V32M16,

1

512Mb DDR SDRAM

Module

Density

256MB

Module

Bandwidth

3.2 GB/s

2.7 GB/s

2.1 GB/s

Memory Clock/

Data Rate

5ns/400 MT/s

6ns/333 MT/s

7.5ns/266 MT/s

Clock Latency

(CL-

t

RCD-

t

RP)

3-3-3

2.5-3-3

Part Number

2

MT4VDDT3264HG-40B__

MT4VDDT3264HY-40B__

MT4VDDT3264HG-335__

MT4VDDT3264HY-335__

MT4VDDT3264HG-265__

Notes:

Configuration

32 Meg x 64

1. The data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions.

Consult

factory for current revision codes. Example: MT4VDDT3264HY-40BF2.

PDF: 09005aef837131bb/Source: 09005aef8086ea0b

dd4c16_32x64h.fm - Rev. E 10/08 EN

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM

Pin Assignments and Descriptions

Table 5:

Pin Assignments

200-Pin SODIMM Front

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

Vref

Vss

DQ0

DQ1

Vdd

DQS0

DQ2

Vss

DQ3

DQ8

Vdd

DQ9

DQS1

Vss

DQ10

DQ11

Vdd

CK0

CK0#

Vss

DQ16

DQ17

Vdd

DQS2

DQ18

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

Vss

DQ19

DQ24

Vdd

DQ25

DQS3

Vss

DQ26

DQ27

Vdd

DNU

Vss

DNU

Vdd

DNU

NC

Vss

DNU

Vdd

NC

A12

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

A9

Vss

A7

A5

A3

A1

Vdd

A10

BA0

WE#

S0#

NC

Vss

DQ32

DQ33

Vdd

DQS4

DQ34

Vss

DQ35

DQ40

Vdd

DQ41

DQS5

Vss

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

DQ42

DQ43

Vdd

Vss

DQ48

DQ49

Vdd

DQS6

DQ50

Vss

DQ51

DQ56

Vdd

DQ57

DQS7

Vss

DQ58

DQ59

Vdd

SDA

SCL

Vddspd

NC

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

Vref

Vss

DQ4

DQ5

Vdd

DM0

DQ6

Vss

DQ7

DQ12

Vdd

DQ13

DM1

Vss

DQ14

DQ15

Vdd

Vss

DQ20

DQ21

Vdd

DM2

DQ22

200-Pin SODIMM Back

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

Vss

DQ23

DQ28

Vdd

DQ29

DM3

Vss

DQ30

DQ31

Vdd

DNU

Vss

DNU

Vdd

DNU

NC

Vss

Vdd

CKE0

NC

A11

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

A8

Vss

A6

A4

A2

A0

Vdd

BA1

RAS#

CAS#

NC

Vss

DQ36

DQ37

Vdd

DM4

DQ38

Vss

DQ39

DQ44

Vdd

DQ45

DM5

Vss

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

DQ46

DQ47

Vdd

CK1#

CK1

Vss

DQ52

DQ53

Vdd

DM6

DQ54

Vss

DQ55

DQ60

Vdd

DQ61

DM7

Vss

DQ62

DQ63

Vdd

SA0

SA1

SA2

NC

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

PDF: 09005aef837131bb/Source: 09005aef8086ea0b

dd4c16_32x64h.fm - Rev. E 10/08 EN

3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM

Pin Assignments and Descriptions

Table 6:

Pin Descriptions

Symbol

A0–A12

Type

Input

Description

Address inputs:

Provide the row address for ACTIVE commands, and the

column address and auto precharge bit (A10) for READ/WRITE commands, to

select one location out of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether the PRECHARGE

applies to one device bank (A10 LOW, device bank selected by BA0 and BA1)

or all device banks (A10 HIGH). The address inputs also provide the op-code

during a MODE REGISTER SET command. BA0 and BA1 define which mode

register (mode register or extended mode register) is loaded during the LOAD

MODE REGISTER command.

Bank address:

BA0 and BA1 define the device bank to which an ACTIVE,

READ, WRITE, or PRECHARGE command is being applied.

Clock:

CK

and

CK#

are differential clock inputs. All control, command, and

address input signals are sampled on the crossing of the positive edge of

CK

and the negative edge of

CK#.

Output data (DQ and DQS) is referenced to the

crossings of

CK

and

CK#.

Clock enable:

CKE

enables (registered HIGH) and

CKE

disables (registered

LOW) the internal clock, input buffers, and output drivers.

Input data mask:

DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH, along with that input data, during a write

access. DM is sampled on both edges of DQS. Although the DM pins are input-

only, the DM loading is designed to match that of the DQ and DQS pins.

Command inputs:

RAS#,

CAS#,

and WE# (along with S#) define the command

being entered.

Chip selects:

S# enables (registered LOW) and disables (registered HIGH) the

command decoder.

Presence-detect address inputs:

These pins are used to configure the SPD

EEPROM address range on the I

2

C

bus.

Serial clock for SPD EEPROM:

SCL is used to synchronize the presence-detect

data transfer to and from the module.

Data input/output:

Data bus.

Data strobe:

Output with read data. Edge-aligned with read data. Input with

write data.

Center-aligned

with write data. Used to capture data.

Serial data:

SDA is a bidirectional pin used to transfer addresses and data into

and out of the presence-detect portion of the module.

Power supply:

+2.5V ±0.2V (-40B: +2.6V ±0.1V).

SPD EEPROM power supply:

+2.3V to +3.6V.

SSTL_2 reference voltage (Vdd/2).

Ground.

No connect:

These pins are not connected on the module.

BA0, BA1

CK0, CK0#,

CK1, CK1#

Input

CKE0

DM0–DM7

Input

RAS#,

CAS#,

WE#

S0#

SA0–SA2

SCL

DQ0–DQ63

DQS0–DQS7

SDA

Vdd

Vddspd

Vref

Vss

NC

Input

I/O

Supply

–

PDF: 09005aef837131bb/Source: 09005aef8086ea0b

dd4c16_32x64h.fm - Rev. E 10/08 EN

4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB (x64, SR) 200-Pin DDR SDRAM SODIMM

Pin Assignments and Descriptions

Figure 2:

S0#

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS#

UDQS

UDM

DQ

LDQS

LDM

DQ

UDQS

UDM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ

LDQS

LDM

DQ

Functional Block Diagram

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

UDQS

UDM

DQ

LDQS

LDM

DQ

CS#

U1

DQS5

DM5

U4

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS2

DM2

CS#

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

UDQS

UDM

DQ

LDQS

LDM

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ

CS#

U2

DQS7

DM7

U5

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

BA0–BA1

A0–A12

RAS#

CAS#

WE#

CKE0

DDR SDRAM

U3

SCL

SPD EEPROM

WP A0 A1 A2

SDA

Vddspd

Vdd

Vref

Vss

SPD EEPROM

DDR SDRAM

Vss

SA0 SA1 SA2

CK0

CK0#

DDR SDRAM U1, U2

CK1

CK1#

DDR SDRAM U4, U5

PDF: 09005aef837131bb/Source: 09005aef8086ea0b

dd4c16_32x64h.fm - Rev. E 10/08 EN

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Reach Compliance Code	unknown
Maximum access time	0.7 ns
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PDMA-N200
memory density	2147483648 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of terminals	200
word count	33554432 words
character code	32000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX64
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIMM
Encapsulate equivalent code	DIMM200,24
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	2.6 V
Certification status	Not Qualified
refresh cycle	8192
Maximum slew rate	1.92 mA
Nominal supply voltage (Vsup)	2.6 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	0.6 mm
Terminal location	DUAL

	MT4VDDT3264HG-40BF2	MT4VDDT3264HY-40BF2
Description	DDR DRAM Module, 32MX64, 0.7ns, CMOS, PDMA200	DDR DRAM Module, 32MX64, 0.7ns, CMOS, LEAD FREE, SODIMM-200
Is it Rohs certified?	incompatible	conform to
Maker	Micron Technology	Micron Technology
Reach Compliance Code	unknown	unknown
Maximum access time	0.7 ns	0.7 ns
Maximum clock frequency (fCLK)	200 MHz	200 MHz
I/O type	COMMON	COMMON
JESD-30 code	R-PDMA-N200	R-XDMA-N200
memory density	2147483648 bit	2147483648 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64
Number of terminals	200	200
word count	33554432 words	33554432 words
character code	32000000	32000000
Maximum operating temperature	70 °C	70 °C
organize	32MX64	32MX64
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	UNSPECIFIED
encapsulated code	DIMM	DIMM
Encapsulate equivalent code	DIMM200,24	DIMM200,24
Package shape	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	2.6 V	2.6 V
Certification status	Not Qualified	Not Qualified
refresh cycle	8192	8192
Maximum slew rate	1.92 mA	1.92 mA
Nominal supply voltage (Vsup)	2.6 V	2.6 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.6 mm	0.6 mm
Terminal location	DUAL	DUAL

MT4VDDT3264HG-40BF2

MT4VDDT3264HG-40BF2 Overview

MT4VDDT3264HG-40BF2 Parametric

Preview

MT4VDDT3264HG-40BF2 Related Products

Recommended Resources