DC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs)
R-DNL
R
WB
Resistor Differential Nonlinearity
3
Resistor Integral Nonlinearity
3
R-INL
R
WB
Resistance Temperature Coefficient
R
WB
/
T
V
DD
= 5 V, I
W
= 100
µA,
Wiper Resistance
R
W
Code = Half-scale
V
DD
= 3 V, I
W
= 100
µA,
Code = Half-scale
Channel Resistance Matching
R
WB
/R
WB
Ch 1 and 2 R
WB
, Dx = 3FF
H
Nominal Resistor Tolerance
R
WB
RESISTOR TERMINALS
Terminal Voltage Range
4
Capacitance
5
Bx
Capacitance Wx
Common-Mode Leakage Current
6
5
V
W, B
C
B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
V
DD
/V
SS
I
DD
I
DD
I
DD(PG)
I
DD(XFR)
I
SS
P
DISS
P
SS
I
1
I
2
e
N_WB
C
T
f = 1 MHz, measured to GND,
Code = Half-scale
f = 1 MHz, measured to GND,
Code = Half-scale
V
W
= V
B
= V
DD
/2
With respect to GND, V
DD
= 5 V
With respect to GND, V
DD
= 5 V
With respect to GND, V
DD
= 3 V
With respect to GND, V
DD
= 3 V
With respect to GND,
V
DD
= +2.5 V, V
SS
= –2.5 V
With respect to GND,
V
DD
= +2.5 V, V
SS
= –2.5 V
R
PULL-UP
= 2.2 kΩ to 5 V
I
OL
= 1.6 mA, V
LOGIC
= 5 V
V
IN
= 0 V or V
DD
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High (SDO, RDY)
Output Logic Low
Input Current
Input Capacitance
5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Positive Supply Current
Programming Mode Current
Read Mode Current
7
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
CURRENT MONITOR TERMINALS
Current Sink at V
19
Current Sink at V
2
DYNAMIC CHARACTERISTICS
5, 10
Resistor Noise Spectral Density
Analog Crosstalk (C
W1
/C
W2
)
8
V
SS
= 0 V
V
IH
= V
DD
or V
IL
= GND,
T
A
= 25
o
C
V
IH
= V
DD
or V
IL
= GND
V
IH
= V
DD
or V
IL
= GND
V
IH
= V
DD
or V
IL
= GND
V
IH
= V
DD
or V
IL
= GND,
V
DD
= +2.5 V, V
SS
= –2.5 V
V
IH
= V
DD
or V
IL
= GND
∆V
DD
= 5 V
±
10%
3.0
±
2.25
2
3.5
35
3
3.5
18
0.002
0.0001
5.5
±
2.75
4.5
6.0
9
6.0
50
0.01
10
10
20/64
0.3
R
WB_FS
= 25 kΩ/250 kΩ, f = 1 kHz
V
B1
= V
B2
= 0 V, Measured V
W1
with
V
W2
= 100 mV p-p @ f = 100 kHz,
Code 1 = Code 2 = 200
H
–65
dB
–2–
REV. B
ADN2850
Parameter
Symbol
Conditions
Min
20
10
1
10
5
5
40
50
50
10
4
0
0.15
35
10
50
140
0.3
Typ
2
Max
Unit
ns
ns
t
CYC
ns
ns
ns
ns
ns
ns
ns
t
CYC
ns
ms
ms
ns
ns
µs
INTERFACE TIMING CHARACTERISTICS (apply to all parts)
5, 11
Clock Cycle Time (t
CYC
)
t
1
CS
Setup Time
t
2
CLK Shutdown Time to
CS
Rise
t
3
Input Clock Pulsewidth
t
4
, t
5
Clock Level High or Low
From Positive CLK Transition
Data Setup Time
t
6
From Positive CLK Transition
Data Hold Time
t
7
CS
to SDO – SPI Line Acquire
t
8
CS
to SDO – SPI Line Release
t
9
t
10
R
P
= 2.2 kΩ, C
L
< 20 pF
CLK to SDO Propagation Delay
12
13
CS
High Pulsewidth
t
12
13
t
13
CS
High to
CS
High
RDY Rise to
CS
Fall
t
14
CS
Rise to RDY Fall Time
t
15
14
t
16
Applies to Command 2
H
, 3
H
, 9
H
Read/Store to Nonvolatile EEMEM
CS
Rise to Clock Edge Setup
t
17
Preset Pulsewidth (Asynchronous)
t
PRW
Not Shown in Timing Diagram
PR
Pulsed Low to Refresh
Preset Response Time to Wiper Setting t
PRESP
Wiper Positions
FLASH/EE MEMORY RELIABILITY
Endurance
15
Data Retention
16
100
100
K Cycles
Years
NOTES
1
Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.
2
Typicals represent average readings at 258C and V
DD
= 5 V.
3
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I
W
~ 50
µA
for V
DD
= 2.7 V and I
W
~ 400
µA
for V
DD
= 5 V.
4
Resistor terminals W and B have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V
DD
/2.
7
Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.
8
P
DISS
is calculated from (I
DD
V
DD
) + (I
SS
V
SS
).
9
Applies to photodiode of optical receiver.
10
All dynamic characteristics use V
DD
= +2.5 V and V
SS
= –2.5 V.
11
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using both V
DD
= 3 V and 5 V.
12
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
. See Applications section.
13
Valid for commands that do not activate the RDY pin.
14
RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at T
A
= –40°C
and V
DD
< 3 V extends the save time to 35 ms.
15
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40
°C,
+25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
16
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will
derate with junction temperature.
Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil 103 mil, 10,197 sq mil.
REV. B
–3–
ADN2850
TIMING DIAGRAMS
CS
CPHA = 1
t
12
t
3
t
2
CLK
CPOL = 1
t
13
t
1
t
5
t
4
t
10
t
17
t
11
LSB OUT
t
8
SDO
t
9
*
MSB
t
7
t
6
SDI
MSB
LSB
t
14
RDY
t
15
t
16
*NOT
DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t
12
t
1
t
2
CLK
CPOL = 0
t
3
t
5
t
17
t
13
t
4
t
8
t
10
t
11
t
9
SDO
MSB OUT
LSB
*
t
7
t
6
SDI
MSB IN
LSB
t
14
RDY
t
15
t
16
*NOT
DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
京公网安备 11010802033920号
EEWORLD
