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CAT24C08VP2I-T3

Description
EEPROM, 1KX8, Serial, CMOS, 2 X 3 MM, GREEN, MO-229, TDFN-8
Categorystorage    storage   
File Size593KB,17 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Environmental Compliance
Download Datasheet Parametric View All

CAT24C08VP2I-T3 Overview

EEPROM, 1KX8, Serial, CMOS, 2 X 3 MM, GREEN, MO-229, TDFN-8

CAT24C08VP2I-T3 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerCatalyst
Parts packaging codeSON
package instructionHVSON,
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)0.4 MHz
JESD-30 codeR-XDSO-N8
JESD-609 codee3
length3 mm
memory density8192 bit
Memory IC TypeEEPROM
memory width8
Humidity sensitivity level1
Number of functions1
Number of terminals8
word count1024 words
character code1000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1KX8
Package body materialUNSPECIFIED
encapsulated codeHVSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/SerialSERIAL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height0.8 mm
Serial bus typeI2C
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1.8 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width2 mm
Maximum write cycle time (tWC)5 ms
CAT24C01/02/04/08/16
FEATURES
Supports Standard and Fast I
2
C Protocol
1.8 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I
2
C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
on I
2
C Bus Inputs (SCL and SDA).
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial and Extended temperature range
RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
For Ordering Information details, see page 16.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
TDFN (VP2)
CAT24C16 / 08 / 04 / 02 / 01
NC / NC / NC / A0 / A0
NC / NC / A1 / A1 / A1
NC / A2 / A2 / A2 / A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
TSOT-23 (TD)
SCL
VSS
SDA
1
2
3
4
VCC
5
WP
SCL
A2, A1, A0
WP
CAT24Cxx
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
NC
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
VSS
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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