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ICS87949AY-01LF

Description
Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Categorylogic    logic   
File Size159KB,13 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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ICS87949AY-01LF Overview

Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

ICS87949AY-01LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts48
Reach Compliance Codecompliant
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQFP-G48
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times15
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.2 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width7 mm
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87949-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
F
EATURES
• 15 single ended LVCMOS outputs, 7Ω typical output
impedance
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
,&6
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
B
LOCK
D
IAGRAM
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
1
DIV_SELA
0
QB0 - QB2
1
DIV_SELB
0
QC0 - QC3
1
DIV_SELC
0
QD0 - QD5
1
DIV_SELD
MR/nOE
0
0
1
1
÷1
÷2
R
0
QA0 - QA1
P
IN
A
SSIGNMENT
GND
GND
GND
GND
V
DDB
V
DDA
V
DDB
QA0
QA1
QB0
QB1
QB2
48 47 46 45 44 43 42 41 40 39 38 37
MR/nOE
CLK_SEL
V
DD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
QD0
V
DDD
QD1
GND
QD2
V
DDD
QD3
GND
QD4
V
DDD
36
35
34
33
32
31
30
29
28
27
26
25
nc
GND
QC0
V
DDC
QC1
GND
QC2
V
DDC
QC3
GND
GND
QD5
ICS87949-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 2, 2002
1

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ICS87949AY-01LF ICS87949AY-01LFT ICS87949AY-01T ICS87949AY-01
Description Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Is it lead-free? Lead free Lead free Contains lead Contains lead
Is it Rohs certified? conform to conform to incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code QFP QFP QFP QFP
package instruction LFQFP, LFQFP, LFQFP, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
Contacts 48 48 48 48
Reach Compliance Code compliant compliant compliant compliant
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code S-PQFP-G48 S-PQFP-G48 S-PQFP-G48 S-PQFP-G48
JESD-609 code e3 e3 e0 e0
length 7 mm 7 mm 7 mm 7 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 1 1 1 1
Number of terminals 48 48 48 48
Actual output times 15 15 15 15
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LFQFP LFQFP LFQFP LFQFP
Package shape SQUARE SQUARE SQUARE SQUARE
Package form FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) 260 260 240 240
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.2 ns 0.2 ns 0.2 ns 0.2 ns
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface MATTE TIN MATTE TIN TIN LEAD TIN LEAD
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.5 mm
Terminal location QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature 30 30 20 20
width 7 mm 7 mm 7 mm 7 mm
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