PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87949-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
F
EATURES
• 15 single ended LVCMOS outputs, 7Ω typical output
impedance
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
,&6
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
B
LOCK
D
IAGRAM
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
1
DIV_SELA
0
QB0 - QB2
1
DIV_SELB
0
QC0 - QC3
1
DIV_SELC
0
QD0 - QD5
1
DIV_SELD
MR/nOE
0
0
1
1
÷1
÷2
R
0
QA0 - QA1
P
IN
A
SSIGNMENT
GND
GND
GND
GND
V
DDB
V
DDA
V
DDB
QA0
QA1
QB0
QB1
QB2
48 47 46 45 44 43 42 41 40 39 38 37
MR/nOE
CLK_SEL
V
DD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
QD0
V
DDD
QD1
GND
QD2
V
DDD
QD3
GND
QD4
V
DDD
36
35
34
33
32
31
30
29
28
27
26
25
nc
GND
QC0
V
DDC
QC1
GND
QC2
V
DDC
QC3
GND
GND
QD5
ICS87949-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 2, 2002
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4, 5
6
7
8
9
10
11
12
13, 14, 18,
22, 26, 27,
31, 35, 39,
43, 44, 48
15, 17,
19, 21,
23, 25
16, 20, 24,
28, 30,
32, 34
29, 33
36
37, 41
38, 40,
42
45, 47
46
Name
MR/nOE
CLK_SEL
V
DD
CLK0, CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Type
Description
Master reset and output enable. Resets outputs to tristate.
Pulldown
Enables and disables all outputs. LVCMOS interface levels.
Clock select input. When HIGH, selects CLK1. When LOW,
Pulldown
selects CLK0. LVCMOS / LVTTL interface levels.
Positive supply pin. Connect to 3.3V.
Pullup
Pullup
LVCMOS / LVTTL clock inputs.
Inver ting differential LVPECL clock input.
for Bank A outputs.
for Bank B outputs.
for Bank C outputs.
for Bank D outputs.
Pulldown Non-inver ting differential LVPECL clock input.
Pulldown PCLK select input.
Controls frequency division
Pulldown
LVCMOS interface levels.
Controls frequency division
Pulldown
LVCMOS interface levels.
Controls frequency division
Pulldown
LVCMOS interface levels.
Controls frequency division
Pulldown
LVCMOS interface levels.
GND
QD0, QD1,
QD2, QD3,
QD4, QD5
V
DDD
QC3, QC2,
QC1, QC0
V
DDC
nc
V
DDB
QB2, QB1,
QB0
QA1, QA0
V
DDA
Power
Power supply ground. Connect to ground.
Output
Power
Output
Power
Unused
Power
Output
Output
Power
Bank D outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank D outputs. Connect to 3.3V or 2.5V.
Bank C outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V.
No connect.
Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V.
Bank B outputs. LVCMOS interface levels.
7Ω typical output impedance.
Bank A outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AY-01
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
Maximum
4
Units
pF
KΩ
KΩ
pF
Ω
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance (per output)
Output Impedance
V
DD
,
*V
DDx
= 3.465V
51
51
TBD
7
Test Conditions
Minimum Typical
*
NOTE: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
, V
DDD
.
T
ABLE
3. F
UNCTION
T
ABLE
MR/nOE
1
0
0
0
0
0
0
0
0
DIV_SELA
X
0
1
X
X
X
X
X
X
Inputs
DIV_SELB
X
X
X
0
1
X
X
X
X
DIV_SELC
X
X
X
X
X
0
1
X
X
DIV_SELD
X
X
X
X
X
X
X
0
1
QA0 - QA1
Hi Z
fIN/1
fIN/2
Active
Active
Active
Active
Active
Active
Outputs
QB0 - QB2 QC0 - QC3
Hi Z
Hi Z
Active
Active
Active
Active
fIN/1
Active
fIN/2
Active
Active
fIN/1
Active
fIN/2
Active
Active
Active
Active
QD0 - QD5
Hi Z
Active
Active
Active
Active
Active
Active
fIN/1
fIN/2
87949AY-01
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
Parameter
V
DD
Positive Supply Voltage
Output Supply Voltage
*V
DDx
Core Supply Current
I
DD
Output Supply Current
**
I
DDx
*V
DDx
denotes V
DDA
, V
DDB
, V
DDC
, V
DDD
.
**
I
DDx
denotes I
DDA
, I
DDB
, I
DDC
, I
DDD
.
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
50
14
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
Parameter
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
CLK0, CLK1
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
IH
Input
High Voltage
V
IL
Input
Low Voltage
I
IH
Input
High Current
*V
DDx
= V
IN
= 3.465V
*V
DDx
= V
IN
= 3.465V
*V
DDx
= 3.465V, V
IN
= 0V
*V
DDx
= 3.465V, V
IN
= 0V
-5
-150
2.6
I
IL
Input
Low Current
V
OH
V
OL
I
OZL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
0.5
TBD
TBD
V
V
V
Output Tristate Current High
I
OZH
NOTE 1: Outputs terminated with 50
Ω
to V
DDx
/2. See page 8, Figure 1A, 3.3V Output Load Test Circuit.
*
NOTE: V
DDx
denotes V
DD
, V
DDA
, V
DDB
, V
DDC
, V
DDD
.
87949AY-01
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 2, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
÷1, ÷2
C
LOCK
G
ENERATOR
Maximum
150
5
Units
µA
µA
µA
µA
1
V
DD
V
V
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
*V
DDx
= V
IN
= 3.465V
*V
DDx
= V
IN
= 3.465V
*V
DDx
= 3.465V, V
IN
= 0V
*V
DDx
= 3.465V, V
IN
= 0V
Minimum
Typical
-5
-150
0.3
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
NOTE:
*V
DDx
denotes V
DD
, V
DDA
, V
DDB
, V
DDC
, V
DDD
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
X
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Input Frequency
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Par t-to-Par t Skew; NOTE 5, 7
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time;NOTE 6
Test Conditions
f
≤
250MHz
f
≤
250MHz
Measured on rising edge at V
DDx
/2
Measured on rising edge at V
DDx
/2
Measured on rising edge at V
DDx
/2
Measured on rising edge at V
DDx
/2
20% to 80%
20% to 80%
f = 10MHz
Minimum
Typical
Maximum
250
Units
MHz
ns
ns
3.5
3.5
100
200
350
500
700
700
50
t
sk(b)
t
sk(o)
t
sk(w)
t
sk(pp)
t
R
t
F
odc
t
EN
ps
ps
ps
ps
ps
ps
%
ns
ns
Output Disable Time;NOTE 6
f = 10MHz
t
DIS
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at V
DDx
/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87949AY-01
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 2, 2002
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