Digital Inputs ...................................................... GND – 0.3V to V
S
+ 0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
MAXIMUM
SPECIFIED
SIGNAL-TO-
INTEGRAL
NO MISSING
(NOISE +
LINEARITY CODE LEVEL DISTORTION)
ERROR (LSB)
(LSB)
RATIO (DB) PACKAGE-LEAD
±3
±2
±3
"
±2
"
15
16
15
"
16
"
85
87
85
"
87
"
Dip-16
PRODUCT
ADS7813P
ADS7813PB
ADS7813U
"
ADS7813UB
"
PACKAGE
DESIGNATOR
N
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
ADS7813P
ADS7813PB
ADS7813U
ADS7813U/1K
TRANSPORT
MEDIA, QUANTITY
Tubes, 25
Tubes, 25
Tubes, 48
Tape and Reel, 1000
Tubes, 48
Tape and Reel, 1000
"
SO-16
"
SO-16
"
"
DW
"
DW
"
–40°C to +85°C ADS7813P
"
ADS7813PB
–40°C to +85°C
"
ADS7813U
"
–40°C to +85°C ADS7813UB
ADS7813UB
"
"
ADS7813UB/1K
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At T
A
= –40°C to +85°C, f
S
= 40kHz, V
S
= +5V
±5%,
using internal reference, unless otherwise specified.
ADS7813P, U
PARAMETER
RESOLUTION
ANALOG INPUT
Voltage Range
Impedance
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
(2)
Full Scale Error
(3)
Full Scale Error Drift
Full Scale Error
(3)
Full Scale Error Drift
Bipolar Zero Error
Bipolar Zero Error Drift
Unipolar Zero Error
Unipolar Zero Error Drift
Recovery Time to Rated Accuracy
from Power Down
(4)
Power Supply Sensitivity
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Useable Bandwidth
(6)
Full Power –3dB Bandwidth
See Table I
See Table I
35
20
25
40
±3
+3, –2
15
0.6
±14
Ext. 2.5000V Ref
Ext. 2.5000V Ref
Bipolar Ranges
Bipolar Ranges
Unipolar Ranges
Unipolar Ranges
1.0µF Capacitor to CAP
+4.75V < (V
S
= +5V) < +5.25
f
IN
=
f
IN
=
f
IN
=
f
IN
=
1kHz
1kHz
1kHz
1kHz
90
85
85
100
–98
89
89
130
600
±5
±3
±3
300
±0.5
✻
±0.5
✻
±10
✻
±6
✻
✻
±12
96
–90
87
87
102
–100
✻
✻
✻
✻
✻
✻
✻
±0.25
16
✻
±0.25
✻
✻
✻
±2
+2, –1
CONDITIONS
MIN
TYP
MAX
16
✻
✻
✻
✻
✻
MIN
ADS7813PB, UB
TYP
MAX
✻
UNITS
Bits
pF
µs
µs
kHz
LSB
(1)
LSB
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
ppm/°C
µs
LSB
dB
(5)
dB
dB
dB
kHz
kHz
Acquire and Convert
–96
2
ADS7813
www.ti.com
SBAS043C
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= –40°C to +85°C, f
S
= 40kHz, V
S
= +5V
±5%,
using internal reference, unless otherwise specified.
ADS7813P, U
PARAMETER
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
(7)
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
Internal Reference Drift
External Reference Voltage Range
External Reference Current Drain
CAP Compensation Capacitors ESR
(8)
DIGITAL INPUTS
Logic Levels
V
IL
V
IH(9)
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
Leakage Current
Output Capacitance
POWER SUPPLY
V
S
Power Dissipation
TEMPERATURE RANGE
Specified Performance
Derated Performance
✻
Same specification as grade to the left.
NOTES: (1) LSB means Least Significant Bit. For the
±10V
input range, one LSB is 305µV.
(2) Typical rms noise at worst case transitions and temperatures.
(3) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the
transition voltage (not divided by the full-scale range) and includes the effect of offset error.
(4) After the ADS7813 is initially powered on and fully settles, this is the time delay after it is brought out of Power Down Mode until all internal
settling occurs and the analog input is acquired to rated accuracy, and normal conversions can begin again.
(5) All specifications in dB are referred to a full-scale input.
(6) Useable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy.
(7) Recovers to specified performance after 2 x FS input overvoltage.
(8) ESR = total equivalent series resistance for the compensation capacitors.
(9) The minimum V
IH
level for the DATACLK signal is 3V.
CONDITIONS
MIN
TYP
40
20
5
750
2.48
2.5
100
8
2.5
2.52
✻
MAX
MIN
ADS7813PB, UB
TYP
✻
✻
✻
✻
✻
✻
✻
✻
✻
MAX
UNITS
ns
ps
µs
ns
V
µA
ppm/°C
V
µA
Ω
FS Step
2.3
V
REF
= +2.5V
2.7
100
3
✻
✻
✻
✻
–0.3
+2.0
+0.8
V
S
+0.3V
±10
±10
✻
✻
✻
✻
✻
✻
V
V
µA
µA
Serial
Binary Two’s Complement
I
SINK
= 1.6mA
I
SOURCE
= 500µA
High-Z State,
V
OUT
= 0V to V
S
High-Z State
+0.4
+4
±1
15
+4.75
f
S
= 40kHz
–40
–55
+5
+5.25
35
+85
+125
✻
✻
✻
✻
15
✻
✻
✻
✻
✻
V
V
µA
pF
V
mW
°C
°C
✻
✻
ADS7813
SBAS043C
www.ti.com
3
PIN CONFIGURATION
PIN #
1
2
3
4
5
6
7
8
9
10
NAME
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
DATACLK
DATA
DESCRIPTION
Analog Input. See Tables I and IV.
Ground
Analog Input. See Tables I and IV.
Analog Input. See Tables I and IV.
Reference Buffer Output. Connect to R1
IN
, R2
IN
, or R3
IN
, as needed.
Reference Buffer Compensation Node. Decouple to ground with a 1µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor.
Reference Input/Output. Outputs internal +2.5V reference via a series 4kΩ resistor. Decouple this voltage with a 1µF to 2.2µF
tantalum capacitor to ground. If an external reference voltage is applied to this pin, it will override the internal reference.
Ground
Data Clock Pin. With EXT/INT LOW, this pin is an output and provides the synchronous clock for the serial data. The output
is tri-stated when CS is HIGH. With EXT/INT HIGH, this pin is an input and the serial data clock must be provided externally.
Serial Data Output. The serial data is always the result of the last completed conversion and is synchronized to DATACLK.
If DATACLK is from the internal clock (EXT/INT LOW), the serial data is valid on both the rising and falling edges of DATACLK.
DATA is tri-stated when CS is HIGH.
External or Internal DATACLK Pin. Selects the source of the synchronous clock for serial data. If HIGH, the clock must be
provided externally. If LOW, the clock is derived from the internal conversion clock. Note that the clock used to time the
conversion is always internal regardless of the status of EXT/INT.
Convert Input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless
of the state of CS. If a conversion is already in progress, the falling edge is ignored. If EXT/INT is LOW, data from the previous
conversion will be serially transmitted during the current conversion.
Chip Select. This input tri-states all outputs when HIGH and enables all outputs when LOW. This includes DATA, BUSY, and
DATACLK (when EXT/INT is LOW). Note that a falling edge on CONV will initiate a conversion even when CS is HIGH.
Busy Output. When a conversion is started, BUSY goes LOW and remains LOW throughout the conversion. If EXT/INT is
LOW, data is serially transmitted while BUSY is LOW. BUSY is tri-stated when CS is HIGH.
Power Down Input. When HIGH, the majority of the ADS7813 is placed in a low power mode and power consumption is
significantly reduced. CONV must be taken LOW prior to PWRD going LOW in order to achieve the lowest power
consumption. The time required for the ADS7813 to return to normal operation after power down depends on a number of
factors. Consult the Power Down section for more information.
+5V Supply Input. For best performance, decouple to ground with a 0.1µF ceramic capacitor in parallel with a 10µF tantalum
capacitor.
11
EXT/INT
12
CONV
13
14
15
CS
BUSY
PWRD
16
V
S
PIN CONFIGURATION
Top View
DIP, SOIC
ANALOG
INPUT
RANGE (V)
±10V
0.3125V to
2.8125V
±5V
CONNECT
R1
IN
TO
V
IN
V
IN
GND
BUF
BUF
V
IN
GND
CONNECT
R2
IN
TO
BUF
V
IN
BUF
GND
V
IN
BUF
V
IN
CONNECT
R3
IN
TO
GND
V
IN
V
IN
V
IN
GND
V
IN
GND
INPUT
IMPEDANCE
(kΩ)
45.7
> 10,000
26.7
26.7
21.3
21.3
21.3
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
1
2
3
4
ADS7813
5
6
7
8
16 V
S
15 PWRD
14 BUSY
13 CS
12 CONV
11 EXT/INT
10 DATA
9
DATACLK
0V to 10V
0V to 4V
±3.33V
0.5V to
4.5V
TABLE I. ADS7813 Input Ranges.
4
ADS7813
www.ti.com
SBAS043C
TYPICAL PERFORMANCE CURVES
At T
A
= +25°C, f
S
= 40kHz, V
S
= +5V,
±10V
input range, using internal reference, unless otherwise noted.
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