PSD412A2M-90J datasheet, PDF - EEWORLD Datasheet

PSD412A2M-90J: DescriptionParallel I/O Port, 40 I/O, CMOS, PQCC68,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，95 Pages; ManufacturerWaferscale Integration Inc.

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PSD412A2M-90J Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

Parameter Name	Attribute value
Maker	Waferscale Integration Inc.
Reach Compliance Code	unknown
Other features	GENERAL PURPOSE ZPLD
maximum clock frequency	41.67 MHz
External data bus width	8
JESD-30 code	S-PQCC-J68
Number of I/O lines	40
Number of ports	5
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
Maximum slew rate	40 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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