EDI88128CS35FM datasheet, PDF - EEWORLD Datasheet

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EDI88128CS35FM: DescriptionStandard SRAM, 128KX8, 35ns, CMOS, CDFP32, CERAMIC, FP-32; Categorystorage storage; File Size232KB，9 Pages; ManufacturerWhite Microelectronics

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EDI88128CS35FM Overview

Standard SRAM, 128KX8, 35ns, CMOS, CDFP32, CERAMIC, FP-32

EDI88128CS35FM Parametric

Parameter Name	Attribute value
Maker	White Microelectronics
package instruction	CERAMIC, FP-32
Reach Compliance Code	unknown
Maximum access time	35 ns
JESD-30 code	R-CDFP-F32
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal location	DUAL

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EDI88128CS

HI-RELIABILITY PRODUCT

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

Access Times of 15*, 17, 20, 25, 35, 45, 55ns

CS and OE Functions for Bus Control

2V Data Retention (EDI88128LPS)

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Organized as 128Kx8

Commercial, Industrial and Military Temperature Ranges

Thru-hole and Surface Mount Packages JEDEC Pinout

• 32 pin Ceramic DIP, 400 mil (Package 102)

• 32 pin Ceramic DIP, 600 mil (Package 9)

• 32 lead Ceramic ZIP (Package 100)

• 32 lead Ceramic SOJ (Package 140)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

Single +5V (±10%) Supply Operation

The EDI88128CS is a high speed, high performance, 128Kx8

megabit density Monolithic CMOS Static RAM.

The device has eight bi-directional input-output lines to provide

simultaneous access to all bits in a word. An automatic power

down feature permits the on-chip circuitry to enter a very low

standby mode and be brought back into operation at a speed equal

to the address access time.

A Low Power version with 2V Data Retention (EDI88128LPS) is

also available for battery back-up opperation. Military product is

available compliant to MIL-PRF-38535.

* 15ns access time is advanced information, contact factory for availability.

FIG. 1

PIN CONFIGURATION

DIP

SOJ

LCC

FLATPACK

PIN DESCRIPTION

I/O

0-7

0-16

Data Inputs/Outputs

Address Inputs

Write Enable

Chip Select

Output Enable

Power (+5V

±10%)

Ground

Not Connected

32 ZIP

TOP VIEW

A16

A14

A12

AØ

I/OØ

I/O1

I/O2

32 V

31 A15

30 NC

29 WE

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

A16

A14

A12

AØ

I/OØ

I/O1

I/O2

TOP VIEW

2 V

A15

10 A13

12 A8

14 A9

16 A11

18 OE

20 A10

22 CS

24 I/O7

26 I/O6

28 I/O5

30 I/O4

32 I/O3

Ø-16

BLOCK DIAGRAM

Memory Array

Address

Buffer

Address

Decoder

I/O

Circuits

I/O

Ø-7

February 2000 Rev. 10

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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