HMT451S6MMP(R)8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 4GB, 512Mx64 Module(2Rank of x8)
4. Absolute Maximum Ratings
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Range
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
5.2 DC & AC Logic Input Levels
5.2.1 For Single-ended Signals
5.2.2 For Differential Signals
5.2.3 Differential Input Cross Point
5.3 Slew Rate Definition
5.3.1 For Ended Input Signals
5.3.2 For Differential Input Signals
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
5.4.2 Differential DC & AC Output Levels
5.4.3 Single Ended Output Slew Rate
5.4.4 Differential Ended Output Slew Rate
5.5 Overshoot/Undershoot Specification
5.5.1 Address and Control Overshoot and Undershoot Specifications
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
5.6 Input/Output Capacitance & AC Parametrics
5.7 IDD Specifications & Measurement Condtiions
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
6.2 DDR3 Standard speed bins and AC para
7. DIMM Outline Diagram
7.1 4GB, 512Mx64 Module(2Rank of x8)
Rev. 0.2 / Apr. 2009
3
HMT451S6MMP(R)8C
1. Description
This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 2Gb M version. DDR3
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM
series based on 2Gb M ver. provide a high performance 8 byte interface in 67.60mm width form factor of industry stan-
dard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• VDDSPD=3.0V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1 and CL-2 sup-
ported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8 banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 82ball
FBGA(x4/x8) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• 8 bit pre-fetch
1.1.2 Ordering Information
# of
DRAMs
16
16
# of
ranks
2
2
Part Name
HMT451S6MMP8C-S6/G7*
HMT451S6MMR8C-S6/G7*
Density
4GB
4GB
Organization
512Mx64
512Mx64
Materials
Lead free
Halogen free
*Information on temperature sensor can be found on the label:
T0
indicates that the DIMM has temperature sensor.
N0
indicates that the DIMM does not have temperature sensor.
Rev. 0.2 / Apr. 2009
4