D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
ADS7800
SBAS001A – OCTOBER 1989 – REVISED FEBRUARY 2004
12-Bit 3
µ
s Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
333k SAMPLES PER SECOND
q
STANDARD
±
10V AND
±
5V INPUT RANGES
q
DC PERFORMANCE OVER TEMP:
No Missing Codes
1/2LSB Integral Linearity Error
3/4LSB Differential Linearity Error
q
AC PERFORMANCE OVER TEMP:
72dB Signal-to-Noise Ratio
80dB Spurious-Free Dynamic Range
–80dB Total Harmonic Distortion
q
INTERNAL SAMPLE/HOLD, REFERENCE,
CLOCK, AND THREE-STATE OUTPUTS
q
POWER DISSIPATION: 215mW max
q
PACKAGE: 24-Pin Single-Wide DIP
24-Lead SOIC
DESCRIPTION
The ADS7800 is a complete 12-bit sampling analog-to-
digital (A/D) converter using state-of-the-art CMOS
structures. It contains a complete 12-bit successive
approximation A/D converter with internal sample/hold,
reference, clock, digital interface for microprocessor
control, and three-state output drivers.
The ADS7800 is specified at a 333kHz sampling rate.
Conversion time is factory set for 2.70µs max over
temperature, and the high-speed sampling input stage
insures a total acquisition and conversion time of 3µs
max over temperature. Precision, laser-trimmed scaling
resistors provide industry-standard input ranges of
±5V
or
±10V.
AC and DC performance are completely specified. Two
grades based on linearity and dynamic performance are
available to provide the optimum price/performance fit in
a wide range of applications.
The 24-pin ADS7800 is available in plastic and side-
braze hermetic 0.3" wide DIPs, and in an SOIC package.
It operates from a +5V supply and either a –12V or –15V
supply. The ADS7800 is available in grades specified
over 0°C to +70°C and –40°C to +85°C temperature
ranges.
Control
Logic
Clock
SAR
Output
Latches
And
Three
State
Drivers
Comparator
BUSY
±10V
IN
±5V
IN
Internal
Ref
CDAC
2V
Reference
Out
Three
State
Parallel
Output
Data
Bus
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1989-2004, Texas Instruments Incorporated
www.ti.com
SPECIFICATIONS
ELECTRICAL
At T
A
= T
MIN
to T
MAX
, Sampling Frequency, f
S
, = 333kHz, –V
S
= –15V, V
S
= +5V, unless otherwise specified.
ADS7800JP/JU/AH
PARAMETER
RESOLUTION
ANALOG INPUT
Voltage Ranges
Impedance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
DC ACCURACY
Full Scale Error
(1)
Full Scale Error Drift
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Bipolar Zero
(1)
Bipolar Zero Drift
Power Supply Sensitivity
–16.5V < –V
S
< –13.5V
–12.6V < –V
S
< –11.4V
+4.75V < V
S
< +5.25V
Transition Noise
(3)
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Two-tone Intermodulation Distortion
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio (SNR)
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
(5)
Overvoltage Recovery
(6)
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Available
for External Loads
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
I
LEAKAGE
(High-Z State)
POWER SUPPLIES
Rated Voltage
–V
S
V
S
(V
SA
and V
SD
)
Current
–I
S
I
S
Power Consumption
1.9
f
IN
= 47kHz
f
IN
= 47kHz
= 24.4kHz (–6dB)
= 28.5kHz (–6dB)
f
IN
= 47kHz
f
IN
= 47kHz
74
0.1
77
–77
–77
70
71
13
150
130
150
2.0
10
2.1
*
77
–74
–74
69
70
±10V/±5V
6.3
4.2
2.5
2.6
380
CONDITIONS
MIN
TYP
MAX
12
*
*
*
*
*
*
ADS7800KP/KU/BH
MIN
TYP
MAX
*
UNITS
Bits
V
kΩ
kΩ
µs
µs
kHz
%
ppm/°C
LSB
(2)
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
dB
(4)
dB
dB
dB
dB
ns
ps, rms
ns
ns
*
V
µA
±10V
Range
±5V
Range
Conversion Alone
Acquisition + Conversion
4.4
2.9
8.1
5.4
2.7
3.0
*
*
*
*
*
*
333
*
±0.50
±0.35
*
±1/2
±3/4
Ensured
±2
*
6
±1
±1
Ensured
±4
1
±1/2
±1/2
±1
*
*
±1/2
*
80
–80
–80
72
73
*
*
*
*
*
*
f
IN1
f
IN2
–77
–77
67
68
–0.3
+2.4
–5
+5
+0.8
+5.3
*
*
*
*
*
*
V
V
µA
µA
I
SINK
= 1.6mA
I
SOURCE
= 500µA
0.0
+2.4
±0.1
Parallel, 12-bit or 8-bit/4-bit
Binary Offset Binary
+0.4
*
+5.0
*
±5
*
*
*
*
V
V
µA
–11.4
+4.75
–15
+5.0
3.5
18
135
–16.5
+5.25
6
25
215
*
*
*
*
*
*
*
*
*
*
*
*
V
V
mA
mA
mW
2
ADS7800
www.ti.com
SBAS001A
SPECIFICATIONS
ELECTRICAL
(CONT)
At T
A
= T
MIN
to T
MAX
, Sampling Frequency, f
S
, = 333kHz, –V
S
= –15V, V
S
= +5V, unless otherwise specified.
ADS7800JP/JU/AH
PARAMETER
TEMPERATURE RANGE
Specification
Operating
Storage
CONDITIONS
JP/JU/KP/KU
AH/BH
JP/KP/JU/KU
MIN
0
–40
–40
–65
TYP
MAX
+70
+85
+85
+150
ADS7800KP/KU/BH
MIN
*
*
*
*
TYP
MAX
*
*
*
*
UNITS
°C
°C
°C
°C
* Same as specification for ADS7800JP/JU/AH.
NOTES: (1) Adjustable to zero with external potentiometer. (2) LSB means Least Significant Bit. For ADS7800, 1LSB = 2.44mV for the
±5V
range, 1LSB =
4.88mV for the
±10V
range. (3) Noise was characterized over temperature near full scale, 0V, and negative full scale. 0.1LSB represents a typical rms level of
noise at the worst case, which was near full scale input at +125°C. (4) All specifications in dB are referred to a full-scale input, either
±10V
or
±5V.
(5) For full
scale step input, 12-bit accuracy attained in specified time. (6) Recovers to specified performance in specified time after 2 x F
S
input overvoltage.
ABSOLUTE MAXIMUM RATINGS
–V
S
to ANALOG COMMON ............................................................ –16.5V
V
S
to DIGITAL COMMON .................................................................... +7V
Pin 23 (V
SD
) to Pin 24 (V
SA
) ...........................................................
±0.3V
ANALOG COMMON to DIGITAL COMMON .......................................
±1V
Control Inputs to DIGITAL COMMON ............................. –0.3 to V
S
+ 0.3V
Analog Input Voltage ..........................................................................
±20V
Maximum Junction Temperature ..................................................... 160°C
Internal Power Dissipation ............................................................. 750mW
Lead Temperature (soldering, 10s) ............................................... +300°C
Thermal Resistance,
θ
JA
:
Plastic DIP ................................................................................ 100°C/W
SOIC ......................................................................................... 100°C/W
Ceramic ...................................................................................... 50°C/W
ELECTROSTATIC
DISCHARGE SENSITIVITY
The ADS7800 is an ESD (electrostatic discharge) sensitive
device. The digital control inputs have a special FET struc-
ture, which turns on when the input exceeds the supply by
18V, to minimize ESD damage. However, permanent damage
may occur on unconnected devices subject to high energy
electrostatic fields. When not in use, devices must be stored in
conductive foam or shunts. The protective foam should be
discharged to the destination socket before devices are re-
moved.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this data
sheet.
ADS7800
SBAS001A
www.ti.com
3
PIN ASSIGNMENTS
PIN # NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
IN1
IN2
REF
AGND
D11
D10
D9
D8
D7
D6
D5
D4
DGND
D3
D2
D1
D0
HBE
DESCRIPTION
±10V
Analog Input. Connected to GND for
±5V
range.
±5V
Analog Input. Connected to GND for
±10V
range.
+2V Reference Output. Bypass to GND with 22µF to
47µF Tantalum. Buffer for external loads.
Analog Ground. Connect to pin 13.
Data Bit 11. Most Significant Bit (MSB).
Data Bit 10.
Data Bit 9.
Data Bit 8.
Data Bit 7 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 6 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.
Digital Ground. Connect to pin 4.
Data Bit 3 if HBE is LOW; Data Bit 11 if HBE is HIGH.
Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH.
Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH.
Data Bit 0 if HBE is LOW. Least Significant Bit (LSB);
Data Bit 8 if HBE is HIGH.
High Byte Enable. When held LOW, data output as 12
bits in parallel. When held HIGH, four MSBs presented on
pins 14-17, pins 9-12 output LOWs. Must be LOW to
initiate conversion.
Read/Convert. Falling edge initiates conversion when CS
is LOW, HBE is LOW, and BUSY is HIGH.
Chip Select. Outputs in Hi-Z state when HIGH. Must be
LOW to initiate conversion or read data.
Busy. Output LOW during conversion. Data valid on rising
edge in Convert Mode.
Negative Power Supply. –12V or –15V. Bypass to GND.
Positive Digital Power Supply. +5V. Connect to pin 24,
and bypass to GND.
Positive Analog Power Supply. +5V. Connect to pin 23,
and bypass to GND.
PIN CONFIGURATION
Top View
DIP/SOIC
IN1
IN2
REF
AGND
D11
D10
D9
D8
D7
D6
D5
D4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
SA
V
SD
–V
S
BUSY
CS
R/C
HBE
D0
D1
D2
D3
DGND
19
20
21
22
23
24
R/C
CS
BUSY
–V
S
V
SD
V
SA
4
ADS7800
www.ti.com
SBAS001A
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
