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PDSP16330BCOAC

Description
Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size87KB,9 Pages
ManufacturerZarlink Semiconductor (Microsemi)
Websitehttp://www.zarlink.com/
Download Datasheet Parametric Compare View All

PDSP16330BCOAC Overview

Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84

PDSP16330BCOAC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerZarlink Semiconductor (Microsemi)
package instructionPGA,
Reach Compliance Codecompliant
boundary scanNO
maximum clock frequency25 MHz
External data bus width16
JESD-30 codeS-CPGA-P84
JESD-609 codee0
length27.94 mm
low power modeNO
Number of terminals84
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width16
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum seat height4.14 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width27.94 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR
PDSP16330/A/B
Pythagoras Processor
DS3884
ISSUE 2.1
November 1998
The PDSP16330 is a high speed digital CMOS IC that
converts Cartesian data (Real and Imaginary) into Polar form
(Magnitude and Phase), at rates up to 20MHz. Cartesian
16+16 bit 2's complement or Sign-Magnitude data is
converted into 16 bit Phase format. The Magnitude output may
be scaled in amplitude by powers of 2. The Phase output
represents a full 2 x
π
field to eliminate phase ambiguities.
Polyimide is used as an inter-layer dielectric and as
glassivation.
The PDSP16330 is offered in three speed grades: a
basic 10MHz part (PDSP16330), a 20MHz version
(PDSP16330A) and a 25MHz version (PDSP16330). A MIL-
STD-883 version is also detailed in a separate datasheet.
PIN 1A INDEX MARK
ON TOP SURFACE
A
B
C
D
E
F
G
H
J
K
L
FEATURES
25MHz Cartesian to Polar Conversion
16-Bit Cartesian Inputs
16-Bit Magnitude Output
12-Bit Phase Output
2’s Complement or Sign-Magnitude Input Formats
Three-state Outputs and Independent
Data Enables Simplify System Interfacing
Magnitude Scaling Facility with Overflow Flag
Less than 400 mW Power Dissipation at 10MHz
84-pin PGA or 100 pin QFP Package or 84 LCC
11 10 9 8 7
6
5 4 3
2 1
AC84
Fig.1 Pin connections - bottom view (PGA)
APPLICATIONS
Digital Signal Processing
Digital Radio
Radar Processing
Sonar Processing
Robotics
ORDERING INFORMATION
Commercial (0
°
C to +70
°
C)
PDSP16330A CO AC
(20MHZ - PGA Package)
PDSP16330B CO AC
(25MHZ - PGA Package)
Industrial (-40
°
C to +85
°
C)
PDSP16330A BO AC
20MHZ - PGA Package
PDSP16330A/IG/GC1R
20MHZ - GC Package
PDSP16330B BO AC
25MHZ - PGA Package
Military (-55
°
C to +125
°
C)
PDSP16330A AO AC
20MHZ - PGA Package
PDSP16330/MC/GC1R
10MHz - GC Package
Mil 883C Screened
GC100
Fig.2 Pin connections - QFP Package
ASSOCIATED PPODUCTS
PDSP16112
PDSP16116
PDSP16318
PDSP16350
PDSP16510A
16 X 12 Complex Multiplier
16 X 16 Complex Multiplier
Complex Accumulator
I/Q Splitter and NCO
Stand Alone FFT Processor

PDSP16330BCOAC Related Products

PDSP16330BCOAC PDSP16330AAOAC PDSP16330BBOAC PDSP16330ABOAC
Description Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84 Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84 Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84 Coordinate Transform Processor, 16-Bit, CMOS, CPGA84, PGA-84
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker Zarlink Semiconductor (Microsemi) Zarlink Semiconductor (Microsemi) Zarlink Semiconductor (Microsemi) Zarlink Semiconductor (Microsemi)
package instruction PGA, PGA, PGA, PGA,
Reach Compliance Code compliant compliant compliant compliant
boundary scan NO NO NO NO
maximum clock frequency 25 MHz 20 MHz 25 MHz 20 MHz
External data bus width 16 16 16 16
JESD-30 code S-CPGA-P84 S-CPGA-P84 S-CPGA-P84 S-CPGA-P84
JESD-609 code e0 e0 e0 e0
length 27.94 mm 27.94 mm 27.94 mm 27.94 mm
low power mode NO NO NO NO
Number of terminals 84 84 84 84
Maximum operating temperature 70 °C 125 °C 85 °C 85 °C
Minimum operating temperature - -55 °C -40 °C -40 °C
Output data bus width 16 16 16 16
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code PGA PGA PGA PGA
Package shape SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Celsius) 225 225 225 225
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.14 mm 4.14 mm 4.14 mm 4.14 mm
Maximum supply voltage 5.25 V 5.05 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.95 V 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V 5 V 5 V
surface mount NO NO NO NO
technology CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL MILITARY INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form PIN/PEG PIN/PEG PIN/PEG PIN/PEG
Terminal pitch 2.54 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location PERPENDICULAR PERPENDICULAR PERPENDICULAR PERPENDICULAR
Maximum time at peak reflow temperature 30 30 30 30
width 27.94 mm 27.94 mm 27.94 mm 27.94 mm
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR DSP PERIPHERAL, COORDINATE TRANSFORM PROCESSOR
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