1H5DU5182EFR
H5DU5162EFR
DESCRIPTION
The H5DU5182EFR and H5DU5162EFR are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ide-
ally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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V
DD
, V
DDQ
= 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
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All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333), 3 (DDR400) and 4 (DDR500) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
t
RAS
lock out function supported
8192
refresh cycles/64ms
60 Ball FBGA Package Type
This product is in compliance with the directive per-
taining of RoHS.
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ORDERING INFORMATION
Part No.
H5DU5182EFR-XXC
H5DU5162EFR-XXC
Configuration
64Mx8
32Mx16
Package
60 Ball
FBGA
OPERATING FREQUENCY
Grade
- FA
- E3
Clock Rate
250MHz@CL4
200MHz@CL3, 166MHz@CL2.5,
133MHz@CL2
Remark
(CL-tRCD-tRP)
DDR500 (4-4-4)
DDR400 (3-3-3),
DDR333 (2.5-3-3),
DDR266A (2-3-3),
DDR266B (2.5-3-3)
DDR333 (2.5-3-3),
DDR266A (2-3-3),
DDR266B (2.5-3-3)
DDR266A (2-3-3),
DDR266B (2.5-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
*X means speed grade
*ROHS (Restriction Of Hazardous Substance)
- J3
166MHz@CL2.5, 133MHz@CL2
- K2
- K3
- L2
133MHz@CL2, 133MHz@CL2.5
133MHz@CL2.5, 100MHz@CL2
100MHz@CL2
* Higher speed part is compatible with the lower speed part.
Rev. 1.0 / Nov. 2009
3
1H5DU5182EFR
H5DU5162EFR
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-
nals, and device input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or
ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for
POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchro-
nous for SELF REFRESH exit, and for output disable. CKE must be maintained
high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK
and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVC-
MOS LOW level after VDD is applied.
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM.
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read,
Write or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the col-
umn address and AUTO PRECHARGE bit for READ/WRITE commands, to select
one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the PRECHARGE applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1. The address inputs also provide the
op code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or
EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command
being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE
access. DM is sampled on both edges of DQS. Although DM pins are input only,
the DM loading matches the DQ and DQS loading. For the x16, LDM corre-
sponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with
read data, centered in write data. Used to capture write data. For the x16,
LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on
DQ8-Q15.
Data input / output pin: Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
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CK, /CK
Input
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A12
Input
/RAS, /CAS, /
WE
Input
DM
(LDM,UDM)
Input
DQS
(LDQS,UDQS)
DQ
VDD/VSS
VDDQ/VSSQ
VREF
NC
Rev. 1.0 / Nov. 2009
I/O
I/O
Supply
Supply
Supply
NC
Microcontroller MCU
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