H5MS5162DFR-K3M datasheet, PDF

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H5MS5162DFR-K3M: Description512Mb (32Mx16bit) Mobile DDR SDRAM; Categorystorage storage; File Size1MB，62 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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H5MS5162DFR-K3M Overview

512Mb (32Mx16bit) Mobile DDR SDRAM

H5MS5162DFR-K3M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	VFBGA, BGA60,9X10,32
Contacts	60
Reach Compliance Code	compli
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	10 mm
memory density	536870912 bi
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA60,9X10,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.00001 A
Maximum slew rate	0.08 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm

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512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O

Specification of

512Mb (32Mx16bit) Mobile DDR SDRAM

Memory Cell Array

- Organized as 4banks of 8,388,608 x16

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.3 / Apr. 2009

Mobile DDR SDRAM 512Mbit (32M x 16bit)

H5MS5162DFR Series

DESCRIPTION

The Hynix H5MS5162DFR Series is 536,870,912-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile

DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones

with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 8,388,608

x16.

The HYNIX H5MS5162DFR series uses a double-data-rate architecture to achieve high-speed operation. The double

data rate architecture is essentially a 2

prefetch architecture with an interface designed to transfer two data per clock

cycle at the I/O pins.

The Hynix H5MS5162DFR Series offers fully synchronous operations referenced to both rising and falling edges of the

clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates

from a differential clock

: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK

data, data strobe and data mask inputs are sampled on both rising and falling edges of it (

Input data is registered on

both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK

). The data

paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible

with LVCMOS.

Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with

the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-

istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits

registered coincident with the READ or WRITE command are used to select the bank and the starting column location

for the burst access.

The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-

tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end

of the burst access.

As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)

allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation

times.

The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which

are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.

A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on

any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-

bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be

used for Read with Autoprecharge enabled and for Write bursts.

Rev 1.3 / Apr. 2009

H5MS5162DFR-K3M Related Products

	H5MS5162DFR-K3M	H5MS5162DFR-E3M	H5MS5162DFR-J3M	H5MS5162DFR-L3M
Description	512Mb (32Mx16bit) Mobile DDR SDRAM	512Mb (32Mx16bit) Mobile DDR SDRAM	512Mb (32Mx16bit) Mobile DDR SDRAM	512Mb (32Mx16bit) Mobile DDR SDRAM
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	VFBGA, BGA60,9X10,32	VFBGA, BGA60,9X10,32	VFBGA, BGA60,9X10,32	VFBGA, BGA60,9X10,32
Contacts	60	60	60	60
Reach Compliance Code	compli	compli	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.5 ns	0.5 ns	0.5 ns	0.5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	200 MHz	166 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60
JESD-609 code	e1	e1	e1	e1
length	10 mm	10 mm	10 mm	10 mm
memory density	536870912 bi	536870912 bi	536870912 bi	536870912 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16	16
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	60	60	60	60
word count	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-30 °C	-30 °C	-30 °C	-30 °C
organize	32MX16	32MX16	32MX16	32MX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA	VFBGA
Encapsulate equivalent code	BGA60,9X10,32	BGA60,9X10,32	BGA60,9X10,32	BGA60,9X10,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
power supply	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192
Maximum seat height	1 mm	1 mm	1 mm	1 mm
self refresh	YES	YES	YES	YES
Continuous burst length	2,4,8	2,4,8	2,4,8	2,4,8
Maximum standby current	0.00001 A	0.00001 A	0.00001 A	0.00001 A
Maximum slew rate	0.08 mA	0.11 mA	0.09 mA	0.08 mA
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm	8 mm

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