HY5Y2B6DLF(P) Series
4Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5Y2B6DLF(P) is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It is organized
as 4banks of 2,097,152x16.
The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of
1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for
special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all
banks.
The Hynix HY5Y2B6DLF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh)
to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automati-
cally adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or
Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power re-
duction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost
all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.
FEATURES
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Standard SDR Protocol
Internal 4bank operation
Voltage : VDD = 3.0V, VDDQ = 3.0V
LVCMOS compatible I/O Interface
Low Voltage interface to reduce I/O power
Low Power Features
- PASR(Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
Programmable CAS latency of 1, 2 or 3
Package : 54 Ball FBGA (Lead, Lead Free)
- HY5Y2B6DLF Seriese : Lead
- HY5Y2B6DLFP Seriese : Lead Free
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ORDERING INFORMATION
Part Number
HY5Y2B6DLF(P)-HE
Clock Frequency
133MHz
CAS
Latency
3
Organization
4banks x 2Mb x 16
Interface
LVCMOS
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.3 / May. 2004
2
HY5Y2B6DLF(P) Series
4Banks x 2M x 16bits Synchronous DRAM
PAD FUNCTION DESCRIPTIONS
Ball Out
F2
F3
G9
G7,G8
H7, H8, J8,
J7, J3, J2,
H3, H2, H1,
G3, H9, G2
F8, F7, F9
F1, E8
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1,
A2
A9, E7, J9,
A1, E3, J1
A7, B3, C7,
D3, A3, B7,
C3, D7
E2, G1
SYMBOL
CLK
CKE
CS
BA0, BA1
TYPE
INPUT
INPUT
INPUT
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the SDR on
the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the SDR
will be one of the states among power down, suspend or self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:Controls output buffers in read mode and masks input data in
write mode
A0 ~ A11
INPUT
RAS, CAS,
WE
UDQM,
LDQM
INPUT
INPUT
DQ0 ~
DQ15
I/O
Data Input/Output:Multiplexed data input/output pin
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/VSSQ
NC
SUPPLY
-
Power supply for output buffers
No connection : These pads should be left unconnected
Rev. 0.3 / May. 2004
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